Various small improvements to synth_xilinx

diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 76d6115ae13c216cad6edd61a349e8a1771a3a75..75d02c828e3cfa6cb303f097959b722e57474982 100644 (file)
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -62,8 +62,8 @@ struct IopadmapPass : public Pass {
                log("\n");
                log("    -bits\n");
                log("        create individual bit-wide buffers even for ports that\n");
-               log("        are wider. (the default behavio is to create word-wide\n");
-               log("        buffers use -widthparam to set the word size on the cell.)\n");
+               log("        are wider. (the default behavior is to create word-wide\n");
+               log("        buffers using -widthparam to set the word size on the cell.)\n");
                log("\n");
        }
        virtual void execute(std::vector<std::string> args, RTLIL::Design *design)

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7b7dbd0fdb15c0f2a508a69a99e792021f676359..a0783740b4f62eababdd14567388afac0cd56e91 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -74,8 +74,7 @@ struct SynthXilinxPass : public Pass {
                log("        techmap -map +/xilinx/brams.v\n");
                log("\n");
                log("    fine:\n");
-               log("        techmap\n");
-               log("        opt -fast -full\n");
+               log("        synth -run fine\n");
                log("\n");
                log("    map_luts:\n");
                log("        abc -lut 6\n");
@@ -91,11 +90,11 @@ struct SynthXilinxPass : public Pass {
                log("\n");
                log("    clkbuf:\n");
                log("        select -set xilinx_clocks <top>/t:FDRE %%x:+FDRE[C] <top>/t:FDRE %%d\n");
-               log("        iopadmap -inpad BUFGP O:I @xilinx_clocks\n");
+               log("        iopadmap -bits -inpad BUFGP O:I @xilinx_clocks\n");
                log("\n");
                log("    iobuf:\n");
                log("        select -set xilinx_nonclocks <top>/w:* <top>/t:BUFGP %%x:+BUFGP[I] %%d\n");
-               log("        iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
+               log("        iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
                log("\n");
                log("    edif:\n");
                log("        write_edif synth.edif\n");
@@ -171,8 +170,7 @@ struct SynthXilinxPass : public Pass {
 
                if (check_label(active, run_from, run_to, "fine"))
                {
-                       Pass::call(design, "techmap");
-                       Pass::call(design, "opt -fast -full");
+                       Pass::call(design, "synth -run fine");
                }
 
                if (check_label(active, run_from, run_to, "map_luts"))
@@ -196,13 +194,13 @@ struct SynthXilinxPass : public Pass {
                if (check_label(active, run_from, run_to, "clkbuf"))
                {
                        Pass::call(design, stringf("select -set xilinx_clocks %s/t:FDRE %%x:+FDRE[C] %s/t:FDRE %%d", top_module.c_str(), top_module.c_str()));
-                       Pass::call(design, "iopadmap -inpad BUFGP O:I @xilinx_clocks");
+                       Pass::call(design, "iopadmap -bits -inpad BUFGP O:I @xilinx_clocks");
                }
 
                if (check_label(active, run_from, run_to, "iobuf"))
                {
                        Pass::call(design, stringf("select -set xilinx_nonclocks %s/w:* %s/t:BUFGP %%x:+BUFGP[I] %%d", top_module.c_str(), top_module.c_str()));
-                       Pass::call(design, "iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks");
+                       Pass::call(design, "iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks");
                }
 
                if (check_label(active, run_from, run_to, "edif"))