ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.

Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 67062be41815a3d7019a54bbeb6f7f6d1d8d1451..87203c3f05b8d83c19163dcded03b6347a3d4c68 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -173,11 +173,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         cpsr.t = pc.thumb() ? 1 : 0;
         return cpsr;
     }
-    if (misc_reg >= MISCREG_CP15_UNIMP_START &&
-        misc_reg < MISCREG_CP15_END) {
+    if (misc_reg >= MISCREG_CP15_UNIMP_START)
         panic("Unimplemented CP15 register %s read.\n",
               miscRegName[misc_reg]);
-    }
+
     switch (misc_reg) {
       case MISCREG_CLIDR:
         warn_once("The clidr register always reports 0 caches.\n");

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 2d47c286ffca178b06a6e2d95d69ae832946568a..c2003fe6d169233b90f7a1266705d9f38e0f9ed7 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -180,6 +180,10 @@ let {{
 
             // Read/write, priveleged only.
           default:
+            if (miscReg >= MISCREG_CP15_UNIMP_START)
+                return new FailUnimplemented(csprintf("%s %s",
+                    isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(),
+                    machInst);
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
             } else {