case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
+ case PIPE_CAP_TEXTURE_QUERY_LOD:
return sws->have_sm4_1;
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
- case PIPE_CAP_TEXTURE_QUERY_LOD:
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
case PIPE_CAP_DRAW_INDIRECT:
}
+/**
+ * Emit Level Of Detail Query (LODQ) instruction.
+ */
+static boolean
+emit_lodq(struct svga_shader_emitter_v10 *emit,
+ const struct tgsi_full_instruction *inst)
+{
+ const uint unit = inst->Src[1].Register.Index;
+
+ assert(emit->version >= 41);
+
+ /* LOD dst, coord, resource, sampler */
+ begin_emit_instruction(emit);
+ emit_opcode(emit, VGPU10_OPCODE_LOD, FALSE);
+ emit_dst_register(emit, &inst->Dst[0]);
+ emit_src_register(emit, &inst->Src[0]); /* coord */
+ emit_resource_register(emit, unit);
+ emit_sampler_register(emit, unit);
+ end_emit_instruction(emit);
+
+ return TRUE;
+}
+
+
/**
* Emit code for TGSI_OPCODE_LOG instruction.
*/
return emit_lg2(emit, inst);
case TGSI_OPCODE_LIT:
return emit_lit(emit, inst);
+ case TGSI_OPCODE_LODQ:
+ return emit_lodq(emit, inst);
case TGSI_OPCODE_LOG:
return emit_log(emit, inst);
case TGSI_OPCODE_LRP: