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fix DDR3 on nexys_video
authorFelix Held <felix-github@felixheld.de>
Fri, 12 Jan 2018 02:33:13 +0000 (13:33 +1100)
committerFelix Held <felix-github@felixheld.de>
Fri, 12 Jan 2018 02:33:13 +0000 (13:33 +1100)
litex/boards/targets/nexys_video.py patch | blob | history

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 77b54688b88b0fb9606b3ae410e46a69254596a7..daa9c9803bc0300e51167cc15ee25ca758a95111 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -97,8 +97,8 @@ class BaseSoC(SoCSDRAM):
 
         # sdram
         self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
-        self.add_constant("A7DDRPHY_BITSLIP", 3)
-        self.add_constant("A7DDRPHY_DELAY", 14)
+        self.add_constant("READ_LEVELING_BITSLIP", 3)
+        self.add_constant("READ_LEVELING_DELAY", 14)
         sdram_module = MT41K256M16(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,