hdl.dsl: fix src_loc_at for FSM state signal.

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index 5c39482f5977eae50317a0cb75d0d919a82988c5..5b820895ba550d07b16f3de24e2c987b48bbcaf8 100644 (file)
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -248,7 +248,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
         self._check_context("FSM", context=None)
         fsm_data = self._set_ctrl("FSM", {
             "name":     name,
-            "signal":   Signal(name="{}_state".format(name)),
+            "signal":   Signal(name="{}_state".format(name), src_loc_at=2),
             "reset":    reset,
             "domain":   domain,
             "encoding": OrderedDict(),