amdgpu/addrlib: Fix invalid access to m_tileTable

Sometimes client driver passes valid tile info into address library,
in this case, the tile index is computed in function
HwlPostCheckTileIndex instead of CiAddrLib::HwlSetupTileCfg.
We need to call HwlPostCheckTileIndex to calculate the correct tile
index to get tile split bytes for this case.

diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 57416dced1663e2a15c1e3e4f66521075db68fba..ccb05282647f3ecb047d5b957ded2c4b531ab92e 100644 (file)
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -1277,14 +1277,25 @@ VOID CiAddrLib::HwlSetupTileInfo(
     {
         if (IsMacroTiled(tileMode))
         {
-            // Non-depth entries store a split factor
-            UINT_32 sampleSplit = m_tileTable[pOut->tileIndex].info.tileSplitBytes;
-            UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
-            UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
+            UINT_32 tileIndex = static_cast<UINT_32>(pOut->tileIndex);
 
-            if (m_rowSize < colorTileSplit)
+            if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
             {
-                pOut->tcCompatible = FALSE;
+                tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex);
+            }
+
+            if (tileIndex != TileIndexInvalid)
+            {
+                ADDR_ASSERT(tileIndex < TileTableSize);
+                // Non-depth entries store a split factor
+                UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
+                UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
+                UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
+
+                if (m_rowSize < colorTileSplit)
+                {
+                    pOut->tcCompatible = FALSE;
+                }
             }
         }
         else