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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index add177fc261d83cab55a9df7f5fc5abd949609ba..12deeaccfb7936d27bd12618ebe9089927dc39c1 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -987,7 +987,7 @@ overlap.
 It is extremely important for implementors to note that the only circumstance
 where upper portions of an underlying 64-bit register are zero'd out is
 when the destination is a scalar.  The ideal register file has byte-level
-write-enable lines, just like most SRAMs.
+write-enable lines, just like most SRAMs, in order to avoid READ-MODIFY-WRITE.
 
 An example ADD operation with predication and element width overrides:
 
@@ -1002,6 +1002,10 @@ An example ADD operation with predication and element width overrides:
         if (RA.isvec)  { irs1 += 1; }
         if (RB.isvec)  { irs2 += 1; }
 
+Thus it can be clearly seen that elements are packed by their
+element width, and the packing starts from the source (or destination)
+specified by the instruction.
+
 # Twin (implicit) result operations
 
 Some operations in the Power ISA already target two 64-bit scalar