intel: Add block alignment for RGTC textures.

We were using the default 4x2 alignment instead of the 4x4 required
for RGTC textures.

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 4a3a2bfada28a7b24dfe115a0e5b399cfcdc6391..f462f32b19a9473cefbc0cbaeb12507c08455acc 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -88,7 +88,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
       GLuint align_w = 4;
 
       mt->total_height = 0;
-      intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
+      intel_get_texture_alignment_unit(mt->format, &align_w, &align_h);
 
       if (mt->compressed) {
           mt->total_width = ALIGN(width, align_w);

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index a96398cc5deb420647a5e354f820a40bf8b483c5..c8ad1a7d34d1eec39097a438edbc2611cd165e78 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -402,8 +402,7 @@ intel_miptree_image_data(struct intel_context *intel,
       if (dst->compressed) {
         unsigned int align_w, align_h;
 
-        intel_get_texture_alignment_unit(dst->internal_format,
-                                         &align_w, &align_h);
+        intel_get_texture_alignment_unit(dst->format, &align_w, &align_h);
         height = (height + align_h - 1) / align_h;
         width = ALIGN(width, align_w);
       }
@@ -445,8 +444,7 @@ intel_miptree_image_copy(struct intel_context *intel,
    if (dst->compressed) {
        GLuint align_w, align_h;
 
-       intel_get_texture_alignment_unit(dst->internal_format,
-                                        &align_w, &align_h);
+       intel_get_texture_alignment_unit(dst->format, &align_w, &align_h);
        height = (height + 3) / 4;
        width = ALIGN(width, align_w);
    }

diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index d39733b6c5a17e09d05f03dae0b7b9bbffd9f699..32c34dad2b17ca83c2744695e382c7d8c57119dc 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -35,32 +35,19 @@
 #include "intel_context.h"
 #include "main/macros.h"
 
-void intel_get_texture_alignment_unit(GLenum internalFormat, GLuint *w, GLuint *h)
+void
+intel_get_texture_alignment_unit(gl_format format,
+                                unsigned int *w, unsigned int *h)
 {
-    switch (internalFormat) {
-    case GL_COMPRESSED_RGB_FXT1_3DFX:
-    case GL_COMPRESSED_RGBA_FXT1_3DFX:
-        *w = 8;
-        *h = 4;
-        break;
-
-    case GL_RGB_S3TC:
-    case GL_RGB4_S3TC:
-    case GL_COMPRESSED_RGB_S3TC_DXT1_EXT:
-    case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT:
-    case GL_RGBA_S3TC:
-    case GL_RGBA4_S3TC:
-    case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT:
-    case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT:
-        *w = 4;
-        *h = 4;
-        break;
-
-    default:
-        *w = 4;
-        *h = 2;
-        break;
-    }
+   if (_mesa_is_format_compressed(format)) {
+      /* The hardware alignment requirements for compressed textures
+       * happen to match the block boundaries.
+       */
+      _mesa_get_format_block_size(format, w, h);
+   } else {
+      *w = 4;
+      *h = 2;
+   }
 }
 
 void i945_miptree_layout_2d(struct intel_context *intel,
@@ -75,7 +62,7 @@ void i945_miptree_layout_2d(struct intel_context *intel,
    GLuint height = mt->height0;
 
    mt->total_width = mt->width0;
-   intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
+   intel_get_texture_alignment_unit(mt->format, &align_w, &align_h);
 
    if (mt->compressed) {
        mt->total_width = ALIGN(mt->width0, align_w);

diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.h b/src/mesa/drivers/dri/intel/intel_tex_layout.h
index 1c8c53e54597db6c58b7ae9c0b1c1b70e95f25fd..b52e5a48855552f531c95e02f926cf9868bbbd87 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.h
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.h
@@ -41,4 +41,5 @@ static INLINE GLuint minify( GLuint d )
 extern void i945_miptree_layout_2d(struct intel_context *intel,
                                   struct intel_mipmap_tree *mt,
                                   uint32_t tiling, int nr_images);
-extern void intel_get_texture_alignment_unit(GLenum, GLuint *, GLuint *);
+void intel_get_texture_alignment_unit(gl_format format,
+                                     unsigned int *w, unsigned int *h);