ecp5: Cells and mappings fixes

Signed-off-by: David Shah <davey1576@gmail.com>

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index cf21ee80e12c11187517bb17b221df52da987cb7..05d44b9b4718c6ba566ede133b195d12ad9de3bd 100644 (file)
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -58,12 +58,12 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
                CCU2C #(
                        .INIT0(16'b0110011010101010),
                        .INIT1(16'b0110011010101010),
-                       .INJECT1_0(1'b0),
-                       .INJECT1_1(1'b0)
+                       .INJECT1_0("NO"),
+                       .INJECT1_1("NO")
           ) ccu2c_i (
                        .CIN(C[i]),
                        .A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
-                       .A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1),
+                       .A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1),
                        .S0(Y[i]), .S1(Y1[i]),
                        .COUT(FCO[i])
                );

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 32aec4e9375371acc6365f95b6527bcf2b41fc56..6c53a78ebc7aefb6fb88c708433d55878227828e 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -103,7 +103,7 @@ module TRELLIS_DPR16X4 (
        integer i;
        initial begin
                for (i = 0; i < 16; i = i + 1)
-                       mem[i] <= INITVAL[4*i :+ 4];
+                       mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
        end
 
        wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
@@ -197,7 +197,7 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
        wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
        wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
 
-       wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+       localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 
        initial Q = srval;