i965: Remove never used RSR and RSL opcodes.

RSR and RSL are listed in the "Defeatured Instructions" section of the
965 PRM, Volume 4:

"The following instructions are removed from Gen4 implementation mainly
 due to implementation cost/schedule reasons.  They are candidates for
 future generations."

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index ec6c854e9062f0bb132911b9079f0fa7926d09d4..7040a270d41a314012831ada6b70a5555350e371 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -691,8 +691,6 @@ enum opcode {
    BRW_OPCODE_XOR =    7,
    BRW_OPCODE_SHR =    8,
    BRW_OPCODE_SHL =    9,
-   BRW_OPCODE_RSR =    10,
-   BRW_OPCODE_RSL =    11,
    BRW_OPCODE_ASR =    12,
    BRW_OPCODE_CMP =    16,
    BRW_OPCODE_CMPN =   17,

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 387450bb025c892e5d1c0bcd88f18918a2c654d8..6ac1c684d21159d00397a1e603abd8d0fd2e1d9c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -154,8 +154,6 @@ ALU2(OR)
 ALU2(XOR)
 ALU2(SHR)
 ALU2(SHL)
-ALU2(RSR)
-ALU2(RSL)
 ALU2(ASR)
 ALU1(F32TO16)
 ALU1(F16TO32)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index ecf8597823f9234c7450915d190c9b97c8c2bb27..f26c913565882cd30127f9ceac3e53f4fcc24433 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -936,8 +936,6 @@ ALU2(OR)
 ALU2(XOR)
 ALU2(SHR)
 ALU2(SHL)
-ALU2(RSR)
-ALU2(RSL)
 ALU2(ASR)
 ALU1(F32TO16)
 ALU1(F16TO32)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index e715c3767b9ef1b41c0c0ff2ad4f9b8881a12abe..ccd4e5edd1e5c6af01ea2576d78ba4d2b6f9d09a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -53,8 +53,6 @@ is_expression(const fs_inst *const inst)
    case BRW_OPCODE_XOR:
    case BRW_OPCODE_SHR:
    case BRW_OPCODE_SHL:
-   case BRW_OPCODE_RSR:
-   case BRW_OPCODE_RSL:
    case BRW_OPCODE_ASR:
    case BRW_OPCODE_ADD:
    case BRW_OPCODE_MUL: