Fix spelling

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 82f149c8c54a0d7198b42496b888aef46d2234e6..4bda388dea3313258e95a6cc24e90c977cec205e 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -924,7 +924,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        else {
                                // Attempt another wideports_split here because there
                                // exists the possibility that different bits of a port
-                               // could be an input and output, therefore parse_xiager()
+                               // could be an input and output, therefore parse_xaiger()
                                // could not combine it into a wideport
                                auto r = wideports_split(w->name.str());
                                wire = module->wire(r.first);