[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Mon, 25 May 2020 00:56:02 +0000 (00:56 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Mon, 25 May 2020 00:56:04 +0000 (01:56 +0100)
d3/c159034d24da26b5e78a83dcd75ee9abf921e9 [new file with mode: 0644]

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+Date: Mon, 25 May 2020 00:56:02 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
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+Message-ID: <bug-336-13-OGQos74Ed4@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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