Misspell

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 1b45085be036ed7b088ad052aa88564a5481ea49..328f0e3c3fa326802fe52fb4bac27fa57cc2eacc 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -567,7 +567,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
                                        // Attempt another wideports_split here because there
                                        // exists the possibility that different bits of a port
-                                       // could be an input and output, therefore parse_xiager()
+                                       // could be an input and output, therefore parse_xaiger()
                                        // could not combine it into a wideport
                                        auto r = wideports_split(w->name.str());
                                        wire = module->wire(r.first);