+2017-08-17 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/rs6000/altivec.md (VParity): Remove TARGET_VSX_TIMODE.
+ * config/rs6000/rs6000-cpus.def: Remove comment.
+ (ISA_2_7_MASKS_SERVER): Delete OPTION_MASK_VSX_TIMODE;
+ (POWERPC_MASKS): Likewise.
+ * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Remove unneeded
+ use of TARGET_VSX_TIMODE.
+ (rs6000_setup_reg_addr_masks): Change TARGET_VSX_TIMODE to TARGET_VSX.
+ (rs6000_init_hard_regno_mode_ok): Remove unneeded uses of
+ TARGET_VSX_TIMODE. Change use of TARGET_VSX_TIMODE to TARGET_VSX.
+ (rs6000_option_override_internal): Remove dead code.
+ (rs6000_legitimize_address): Change TARGET_VSX_TIMODE to TARGET_VSX.
+ (rs6000_legitimize_reload_address): Likewise.
+ (rs6000_legitimate_address_p): Likewise.
+ (rs6000_opt_masks): Delete "vsx-timode".
+ (rs6000_disable_incompatible_switches): Remove mention of -mvsx-timode
+ from function comment.
+ * config/rs6000/rs6000.h (MASK_VSX_TIMODE): Delete.
+ * config/rs6000/rs6000.md (FMOVE128_GPR): Remove TARGET_VSX_TIMODE.
+ (V16QI, V8HI, V4SI, V4SF, V2DI, V2DF, V1TI): Remove useless empty
+ condition.
+ * config/rs6000/rs6000.opt (mvsx-timode): Replace with stub.
+ * config/rs6000/vector.md (VEC_IP): Remove TARGET_VSX_TIMODE.
+ * config/rs6000/vsx.md (VSX_LE_128): Likewise.
+ (VSX_TI): Likewise.
+ (VSX_M): Likewise.
+ (define_peephole2): Likewise.
+
2017-08-17 Martin Sebor <msebor@redhat.com>
PR c/81859
(define_mode_iterator VParity [V4SI
V2DI
V1TI
- (TI "TARGET_VSX_TIMODE")])
+ TI])
(define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")])
(define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")])
/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
altivec is a win so enable it. */
- /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
- PR 58587 is fixed. */
#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FLOAT128_TYPE \
- | OPTION_MASK_P8_VECTOR \
- | OPTION_MASK_VSX_TIMODE)
+ | OPTION_MASK_P8_VECTOR)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_TOC_FUSION \
- | OPTION_MASK_VSX \
- | OPTION_MASK_VSX_TIMODE)
+ | OPTION_MASK_VSX)
#endif
&& (VECTOR_MEM_VSX_P (mode)
|| FLOAT128_VECTOR_P (mode)
|| reg_addr[mode].scalar_in_vmx_p
- || (TARGET_VSX_TIMODE && mode == TImode)
+ || mode == TImode
|| (TARGET_VADDUQM && mode == V1TImode)))
{
if (FP_REGNO_P (regno))
else if ((addr_mask != 0) && !indexed_only_p
&& msize == 16 && TARGET_P9_DFORM_VECTOR
&& (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
- || (m2 == TImode && TARGET_VSX_TIMODE)))
+ || (m2 == TImode && TARGET_VSX)))
{
addr_mask |= RELOAD_REG_OFFSET;
if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
}
/* Allow TImode in VSX register and set the VSX memory macros. */
- if (TARGET_VSX && TARGET_VSX_TIMODE)
+ if (TARGET_VSX)
{
rs6000_vector_mem[TImode] = VECTOR_VSX;
rs6000_vector_align[TImode] = align64;
rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
-
- if (TARGET_VSX_TIMODE)
- rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
+ rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
}
/* Add conditional constraints based on various options, to allow us to
reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
}
- if (TARGET_VSX_TIMODE)
+ if (TARGET_VSX)
{
reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
}
- if (TARGET_VSX_TIMODE)
+ if (TARGET_VSX)
{
reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
}
}
- if (TARGET_VSX_TIMODE && !TARGET_VSX)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE)
- error ("%qs requires %qs", "-mvsx-timode", "-mvsx");
- rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE;
- }
-
if (TARGET_DFP && !TARGET_HARD_FLOAT)
{
if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
}
}
- /* Enable -mvsx-timode by default if VSX. */
- if (TARGET_VSX && !TARGET_VSX_TIMODE
- && (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) == 0)
- rs6000_isa_flags |= OPTION_MASK_VSX_TIMODE;
-
/* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
support. If we only have ISA 2.06 support, and the user did not specify
the switch, leave it set to -1 so the movmisalign patterns are enabled,
pointer, so it works with both GPRs and VSX registers. */
/* Make sure both operands are registers. */
else if (GET_CODE (x) == PLUS
- && (mode != TImode || !TARGET_VSX_TIMODE))
+ && (mode != TImode || !TARGET_VSX))
return gen_rtx_PLUS (Pmode,
force_reg (Pmode, XEXP (x, 0)),
force_reg (Pmode, XEXP (x, 1)));
&& mode != TDmode
&& mode != IFmode
&& mode != KFmode
- && (mode != TImode || !TARGET_VSX_TIMODE)
+ && (mode != TImode || !TARGET_VSX)
&& mode != PTImode
&& (mode != DImode || TARGET_POWERPC64)
&& ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
go into VSX registers, so we allow REG+REG, while TImode seems
somewhat split, in that some uses are GPR based, and some VSX based. */
/* FIXME: We could loosen this by changing the following to
- if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE)
+ if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
but currently we cannot allow REG+REG addressing for TImode. See
PR72827 for complete details on how this ends up hoodwinking DSE. */
- if (mode == TImode && TARGET_VSX_TIMODE)
+ if (mode == TImode && TARGET_VSX)
return 0;
/* If not REG_OK_STRICT (before reload) let pass any stack offset. */
if (! reg_ok_strict
{ "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
{ "aix64", OPTION_MASK_64BIT, false, false },
/* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
- -mvsx-timode, -mupper-regs-df).
+ -mupper-regs-df, etc.).
If the user used -mno-power8-vector, we need to turn off all of the implicit
ISA 2.07 and 3.0 options that relate to the vector unit.
#define MASK_STRING OPTION_MASK_STRING
#define MASK_UPDATE OPTION_MASK_UPDATE
#define MASK_VSX OPTION_MASK_VSX
-#define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE
#ifndef IN_LIBGCC2
#define MASK_POWERPC64 OPTION_MASK_POWERPC64
(TD "TARGET_HARD_FLOAT")])
; Iterators for 128 bit types for direct move
-(define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
- (V16QI "")
- (V8HI "")
- (V4SI "")
- (V4SF "")
- (V2DI "")
- (V2DF "")
- (V1TI "")
+(define_mode_iterator FMOVE128_GPR [TI
+ V16QI
+ V8HI
+ V4SI
+ V4SF
+ V2DI
+ V2DF
+ V1TI
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
Save the TOC in the prologue for indirect calls rather than inline.
+; This option existed in the past, but now is always the same as -mvsx.
mvsx-timode
-Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags)
-Allow 128-bit integers in VSX registers.
+Target RejectNegative Undocumented Ignore
mpower8-fusion
Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
V4SI
V2DI
V1TI
- (TI "TARGET_VSX_TIMODE")])
+ TI])
;; Vector float modes
(define_mode_iterator VEC_F [V4SF V2DF])
;; types that goes in a single vector register.
(define_mode_iterator VSX_LE_128 [(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")
- (TI "TARGET_VSX_TIMODE")
+ TI
V1TI])
;; Iterator for 128-bit integer types that go in a single vector register.
-(define_mode_iterator VSX_TI [(TI "TARGET_VSX_TIMODE") V1TI])
+(define_mode_iterator VSX_TI [TI V1TI])
;; Iterator for the 2 32-bit vector types
(define_mode_iterator VSX_W [V4SF V4SI])
V1TI
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")
- (TI "TARGET_VSX_TIMODE")])
+ TI])
;; Map into the appropriate load/store name based on the type
(define_mode_attr VSm [(V16QI "vw4")
(set (match_operand:VSX_TI 2 "int_reg_operand")
(rotate:VSX_TI (match_dup 0)
(const_int 64)))]
- "!BYTES_BIG_ENDIAN && TARGET_VSX && TARGET_VSX_TIMODE && !TARGET_P9_VECTOR
+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR
&& (rtx_equal_p (operands[0], operands[2])
|| peep2_reg_dead_p (2, operands[0]))"
[(set (match_dup 2) (match_dup 1))])
(set (match_operand:VSX_TI 2 "memory_operand")
(rotate:VSX_TI (match_dup 0)
(const_int 64)))]
- "!BYTES_BIG_ENDIAN && TARGET_VSX && TARGET_VSX_TIMODE && !TARGET_P9_VECTOR
+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
(set (match_operand:TI 2 "vsx_register_operand" "")
(rotate:TI (match_dup 0)
(const_int 64)))]
- "!BYTES_BIG_ENDIAN && TARGET_VSX && TARGET_VSX_TIMODE && !TARGET_P9_VECTOR
+ "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR
&& (rtx_equal_p (operands[0], operands[2])
|| peep2_reg_dead_p (2, operands[0]))"
[(set (match_dup 2) (match_dup 1))])
+2017-08-17 Peter Bergner <bergner@vnet.ibm.com>
+
+ * gcc.target/powerpc/p8vector-int128-1.c: Remove use of -mvsx-timode.
+ * gcc.target/powerpc/p9-vparity.c: Likewise.
+ * gcc.target/powerpc/pr68805.c: Likewise.
+ * gcc.target/powerpc/pr80098-4.c: Remove useless test case.
+
2017-08-17 Peter Bergner <bergner@vnet.ibm.com>
PR target/72804
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */
+/* { dg-options "-mcpu=power8 -O3" } */
#include <altivec.h>
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-timode" } */
+/* { dg-options "-mcpu=power9 -O2" } */
#include <altivec.h>
/* { dg-do compile { target powerpc64le-*-* } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-O2 -mvsx-timode -mcpu=power8" } */
+/* { dg-options "-O2 -mcpu=power8" } */
typedef struct bar {
void *a;
+++ /dev/null
-/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mcpu=power7 -mno-vsx -mvsx-timode" } */
-
-int i;
-
-/* { dg-error "'-mno-vsx' turns off '-mvsx-timode'" "PR80098" { target *-*-* } 0 } */
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