* gas/mips/mips4.s, gas/mips/mips4.d: Use $fccN for condition code

	registers.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index f5038cb87da7fb22d1facf7955513d9ed5981a02..6a1964a26183fdc4162b4091798a472010005fdb 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+Mon Sep  9 14:37:00 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+       * gas/mips/mips4.s, gas/mips/mips4.d: Use $fccN for condition code
+       registers.
+
+Fri Sep  6 18:23:54 1996  James G. Smith  <jsmith@cygnus.co.uk>
+
+       * gas/mips/dli.{s,d}: More test cases added.
+
 Wed Sep  4 11:47:29 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
        * gas/mips/mips.exp: Add check for dli macro instruction.

diff --git a/gas/testsuite/gas/mips/mips4.s b/gas/testsuite/gas/mips/mips4.s
new file mode 100644 (file)
index 0000000..7b7b634
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips4.s
@@ -0,0 +1,47 @@
+# Source file used to test -mips4 instructions.
+
+text_label:    
+       bc1f    text_label
+       bc1f    $fcc1,text_label
+       bc1fl   $fcc1,text_label
+       bc1t    $fcc1,text_label
+       bc1tl   $fcc2,text_label
+       c.f.d   $f4,$f6
+       c.f.d   $fcc1,$f4,$f6
+       ldxc1   $f2,$4($5)
+       lwxc1   $f2,$4($5)
+       madd.d  $f0,$f2,$f4,$f6
+       madd.s  $f0,$f2,$f4,$f6
+       movf    $4,$5,$fcc4
+       movf.d  $f4,$f6,$fcc0
+       movf.s  $f4,$f6,$fcc0
+       movn    $4,$6,$6
+       movn.d  $f4,$f5,$6
+       movn.s  $f4,$f5,$6
+       movt    $4,$5,$fcc4
+       movt.d  $f4,$f6,$fcc0
+       movt.s  $f4,$f6,$fcc0
+       movz    $4,$6,$6
+       movz.d  $f4,$f5,$6
+       movz.s  $f4,$f5,$6
+       msub.d  $f0,$f2,$f4,$f6
+       msub.s  $f0,$f2,$f4,$f6
+       nmadd.d $f0,$f2,$f4,$f6
+       nmadd.s $f0,$f2,$f4,$f6
+       nmsub.d $f0,$f2,$f4,$f6
+       nmsub.s $f0,$f2,$f4,$f6
+
+       # We don't test pref because currently the disassembler will
+       # disassemble it as lwc3.  lwc3 is correct for mips1 to mips3,
+       # while pref is correct for mips4.  Unfortunately, the
+       # disassembler does not know which architecture it is
+       # disassembling for.
+       # pref  4,0($4)
+
+       prefx   4,$4($5)
+       recip.d $f4,$f6
+       recip.s $f4,$f6
+       rsqrt.d $f4,$f6
+       rsqrt.s $f4,$f6
+       sdxc1   $f4,$4($5)
+       swxc1   $f4,$4($5)