#include "sim-config.h"
extern int ctrl_c;
-extern int32 sis_verbose;
-extern int32 sparclite, sparclite_board;
+extern int32_t sis_verbose;
+extern int32_t sparclite, sparclite_board;
extern int rom8,wrp,uben;
extern char uart_dev1[], uart_dev2[];
/* MEC registers */
static char fname[256];
-static int32 find = 0;
-static uint32 mec_ssa[2]; /* Write protection start address */
-static uint32 mec_sea[2]; /* Write protection end address */
-static uint32 mec_wpr[2]; /* Write protection control fields */
-static uint32 mec_sfsr;
-static uint32 mec_ffar;
-static uint32 mec_ipr;
-static uint32 mec_imr;
-static uint32 mec_isr;
-static uint32 mec_icr;
-static uint32 mec_ifr;
-static uint32 mec_mcr; /* MEC control register */
-static uint32 mec_memcfg; /* Memory control register */
-static uint32 mec_wcr; /* MEC waitstate register */
-static uint32 mec_iocr; /* MEC IO control register */
-static uint32 posted_irq;
-static uint32 mec_ersr; /* MEC error and status register */
-static uint32 mec_tcr; /* MEC test comtrol register */
-
-static uint32 rtc_counter;
-static uint32 rtc_reload;
-static uint32 rtc_scaler;
-static uint32 rtc_scaler_start;
-static uint32 rtc_enabled;
-static uint32 rtc_cr;
-static uint32 rtc_se;
-
-static uint32 gpt_counter;
-static uint32 gpt_reload;
-static uint32 gpt_scaler;
-static uint32 gpt_scaler_start;
-static uint32 gpt_enabled;
-static uint32 gpt_cr;
-static uint32 gpt_se;
-
-static uint32 wdog_scaler;
-static uint32 wdog_counter;
-static uint32 wdog_rst_delay;
-static uint32 wdog_rston;
+static int32_t find = 0;
+static uint32_t mec_ssa[2]; /* Write protection start address */
+static uint32_t mec_sea[2]; /* Write protection end address */
+static uint32_t mec_wpr[2]; /* Write protection control fields */
+static uint32_t mec_sfsr;
+static uint32_t mec_ffar;
+static uint32_t mec_ipr;
+static uint32_t mec_imr;
+static uint32_t mec_isr;
+static uint32_t mec_icr;
+static uint32_t mec_ifr;
+static uint32_t mec_mcr; /* MEC control register */
+static uint32_t mec_memcfg; /* Memory control register */
+static uint32_t mec_wcr; /* MEC waitstate register */
+static uint32_t mec_iocr; /* MEC IO control register */
+static uint32_t posted_irq;
+static uint32_t mec_ersr; /* MEC error and status register */
+static uint32_t mec_tcr; /* MEC test comtrol register */
+
+static uint32_t rtc_counter;
+static uint32_t rtc_reload;
+static uint32_t rtc_scaler;
+static uint32_t rtc_scaler_start;
+static uint32_t rtc_enabled;
+static uint32_t rtc_cr;
+static uint32_t rtc_se;
+
+static uint32_t gpt_counter;
+static uint32_t gpt_reload;
+static uint32_t gpt_scaler;
+static uint32_t gpt_scaler_start;
+static uint32_t gpt_enabled;
+static uint32_t gpt_cr;
+static uint32_t gpt_se;
+
+static uint32_t wdog_scaler;
+static uint32_t wdog_counter;
+static uint32_t wdog_rst_delay;
+static uint32_t wdog_rston;
enum wdog_type {
init, disabled, enabled, stopped
/* Memory support variables */
-static uint32 mem_ramr_ws; /* RAM read waitstates */
-static uint32 mem_ramw_ws; /* RAM write waitstates */
-static uint32 mem_romr_ws; /* ROM read waitstates */
-static uint32 mem_romw_ws; /* ROM write waitstates */
-static uint32 mem_ramstart; /* RAM start */
-static uint32 mem_ramend; /* RAM end */
-static uint32 mem_rammask; /* RAM address mask */
-static uint32 mem_ramsz; /* RAM size */
-static uint32 mem_romsz; /* ROM size */
-static uint32 mem_accprot; /* RAM write protection enabled */
-static uint32 mem_blockprot; /* RAM block write protection enabled */
+static uint32_t mem_ramr_ws; /* RAM read waitstates */
+static uint32_t mem_ramw_ws; /* RAM write waitstates */
+static uint32_t mem_romr_ws; /* ROM read waitstates */
+static uint32_t mem_romw_ws; /* ROM write waitstates */
+static uint32_t mem_ramstart; /* RAM start */
+static uint32_t mem_ramend; /* RAM end */
+static uint32_t mem_rammask; /* RAM address mask */
+static uint32_t mem_ramsz; /* RAM size */
+static uint32_t mem_romsz; /* ROM size */
+static uint32_t mem_accprot; /* RAM write protection enabled */
+static uint32_t mem_blockprot; /* RAM block write protection enabled */
static unsigned char romb[ROM_SZ];
static unsigned char ramb[RAM_END - RAM_START];
/* UART support variables */
-static int32 fd1, fd2; /* file descriptor for input file */
-static int32 Ucontrol; /* UART status register */
+static int32_t fd1, fd2; /* file descriptor for input file */
+static int32_t Ucontrol; /* UART status register */
static unsigned char aq[UARTBUF], bq[UARTBUF];
-static int32 anum, aind = 0;
-static int32 bnum, bind = 0;
+static int32_t anum, aind = 0;
+static int32_t bnum, bind = 0;
static char wbufa[UARTBUF], wbufb[UARTBUF];
static unsigned wnuma;
static unsigned wnumb;
static int f1open = 0, f2open = 0;
static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
-static uint32 uart_stat_reg;
-static uint32 uarta_data, uartb_data;
+static uint32_t uart_stat_reg;
+static uint32_t uarta_data, uartb_data;
#ifdef ERA
int era = 0;
static void decode_mcr (void);
static void close_port (void);
static void mec_reset (void);
-static void mec_intack (int32 level);
+static void mec_intack (int32_t level);
static void chk_irq (void);
-static void mec_irq (int32 level);
-static void set_sfsr (uint32 fault, uint32 addr,
- uint32 asi, uint32 read);
-static int32 mec_read (uint32 addr, uint32 asi, uint32 *data);
-static int mec_write (uint32 addr, uint32 data);
+static void mec_irq (int32_t level);
+static void set_sfsr (uint32_t fault, uint32_t addr,
+ uint32_t asi, uint32_t read);
+static int32_t mec_read (uint32_t addr, uint32_t asi, uint32_t *data);
+static int mec_write (uint32_t addr, uint32_t data);
static void port_init (void);
-static uint32 read_uart (uint32 addr);
-static void write_uart (uint32 addr, uint32 data);
+static uint32_t read_uart (uint32_t addr);
+static void write_uart (uint32_t addr, uint32_t data);
static void flush_uart (void);
static void uarta_tx (void);
static void uartb_tx (void);
static void wdog_start (void);
static void rtc_intr (void *arg);
static void rtc_start (void);
-static uint32 rtc_counter_read (void);
-static void rtc_scaler_set (uint32 val);
-static void rtc_reload_set (uint32 val);
+static uint32_t rtc_counter_read (void);
+static void rtc_scaler_set (uint32_t val);
+static void rtc_reload_set (uint32_t val);
static void gpt_intr (void *arg);
static void gpt_start (void);
-static uint32 gpt_counter_read (void);
-static void gpt_scaler_set (uint32 val);
-static void gpt_reload_set (uint32 val);
-static void timer_ctrl (uint32 val);
-static void * get_mem_ptr (uint32 addr, uint32 size);
-static void store_bytes (unsigned char *mem, uint32 waddr,
- uint32 *data, int sz, int32 *ws);
+static uint32_t gpt_counter_read (void);
+static void gpt_scaler_set (uint32_t val);
+static void gpt_reload_set (uint32_t val);
+static void timer_ctrl (uint32_t val);
+static void * get_mem_ptr (uint32_t addr, uint32_t size);
+static void store_bytes (unsigned char *mem, uint32_t waddr,
+ uint32_t *data, int sz, int32_t *ws);
extern int ext_irl;
/* IU error mode manager */
void
-error_mode(uint32 pc)
+error_mode(uint32_t pc)
{
mec_ersr |= 0x1;
static void
-mec_intack(int32 level)
+mec_intack(int32_t level)
{
int irq_test;
static void
chk_irq(void)
{
- int32 i;
- uint32 itmp;
+ int32_t i;
+ uint32_t itmp;
int old_irl;
old_irl = ext_irl;
}
static void
-mec_irq(int32 level)
+mec_irq(int32_t level)
{
mec_ipr |= (1 << level);
chk_irq();
}
static void
-set_sfsr(uint32 fault, uint32 addr, uint32 asi, uint32 read)
+set_sfsr(uint32_t fault, uint32_t addr, uint32_t asi, uint32_t read)
{
if ((asi == 0xa) || (asi == 0xb)) {
mec_ffar = addr;
}
}
-static int32
-mec_read(uint32 addr, uint32 asi, uint32 *data)
+static int32_t
+mec_read(uint32_t addr, uint32_t asi, uint32_t *data)
{
switch (addr & 0x0ff) {
}
static int
-mec_write(uint32 addr, uint32 data)
+mec_write(uint32_t addr, uint32_t data)
{
if (sis_verbose > 1)
printf("MEC write a: %08x, d: %08x\n",addr,data);
}
-static uint32
-read_uart(uint32 addr)
+static uint32_t
+read_uart(uint32_t addr)
{
unsigned tmp;
if (aind < anum) {
if ((aind + 1) < anum)
mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
+ return (0x700 | (uint32_t) aq[aind++]);
} else {
if (f1open) {
anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
aind = 0;
if ((aind + 1) < anum)
mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
+ return (0x700 | (uint32_t) aq[aind++]);
} else {
- return (0x600 | (uint32) aq[aind]);
+ return (0x600 | (uint32_t) aq[aind]);
}
}
if (bind < bnum) {
if ((bind + 1) < bnum)
mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
+ return (0x700 | (uint32_t) bq[bind++]);
} else {
if (f2open) {
bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
bind = 0;
if ((bind + 1) < bnum)
mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
+ return (0x700 | (uint32_t) bq[bind++]);
} else {
- return (0x600 | (uint32) bq[bind]);
+ return (0x600 | (uint32_t) bq[bind]);
}
}
}
static void
-write_uart(uint32 addr, uint32 data)
+write_uart(uint32_t addr, uint32_t data)
{
unsigned char c;
static void
uart_rx(void *arg)
{
- int32 rsize;
+ int32_t rsize;
char rxd;
rtc_enabled = 1;
}
-static uint32
+static uint32_t
rtc_counter_read(void)
{
return rtc_counter;
}
static void
-rtc_scaler_set(uint32 val)
+rtc_scaler_set(uint32_t val)
{
rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
}
static void
-rtc_reload_set(uint32 val)
+rtc_reload_set(uint32_t val)
{
rtc_reload = val;
}
gpt_enabled = 1;
}
-static uint32
+static uint32_t
gpt_counter_read(void)
{
return gpt_counter;
}
static void
-gpt_scaler_set(uint32 val)
+gpt_scaler_set(uint32_t val)
{
gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
}
static void
-gpt_reload_set(uint32 val)
+gpt_reload_set(uint32_t val)
{
gpt_reload = val;
}
static void
-timer_ctrl(uint32 val)
+timer_ctrl(uint32_t val)
{
rtc_cr = ((val & TCR_TCRCR) != 0);
wait-states. */
static void
-store_bytes (unsigned char *mem, uint32 waddr, uint32 *data, int32 sz,
- int32 *ws)
+store_bytes (unsigned char *mem, uint32_t waddr, uint32_t *data, int32_t sz,
+ int32_t *ws)
{
switch (sz) {
case 0:
/* Memory emulation */
int
-memory_iread (uint32 addr, uint32 *data, uint32 *ws)
+memory_iread (uint32_t addr, uint32_t *data, uint32_t *ws)
{
- uint32 asi;
+ uint32_t asi;
if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
*ws = mem_ramr_ws;
}
int
-memory_read(int32 asi, uint32 addr, void *data, int32 sz, int32 *ws)
+memory_read(int32_t asi, uint32_t addr, void *data, int32_t sz, int32_t *ws)
{
- int32 mexc;
+ int32_t mexc;
#ifdef ERRINJ
if (errmec) {
}
int
-memory_write(int32 asi, uint32 addr, uint32 *data, int32 sz, int32 *ws)
+memory_write(int32_t asi, uint32_t addr, uint32_t *data, int32_t sz, int32_t *ws)
{
- uint32 byte_addr;
- uint32 byte_mask;
- uint32 waddr;
- uint32 *ram;
- int32 mexc;
+ uint32_t byte_addr;
+ uint32_t byte_mask;
+ uint32_t waddr;
+ uint32_t *ram;
+ int32_t mexc;
int i;
int wphit[2];
}
static void *
-get_mem_ptr(uint32 addr, uint32 size)
+get_mem_ptr(uint32_t addr, uint32_t size)
{
if ((addr + size) < ROM_SZ) {
return &romb[addr];
}
int
-sis_memory_write(uint32 addr, const void *data, uint32 length)
+sis_memory_write(uint32_t addr, const void *data, uint32_t length)
{
void *mem;
}
int
-sis_memory_read(uint32 addr, void *data, uint32 length)
+sis_memory_read(uint32_t addr, void *data, uint32_t length)
{
char *mem;
#include <math.h>
#include <stdio.h>
-extern int32 sis_verbose, sparclite;
+extern int32_t sis_verbose, sparclite;
int ext_irl = 0;
/* Load/store interlock delay */
/* Forward declarations */
-static uint32 sub_cc (uint32 psr, int32 operand1, int32 operand2,
- int32 result);
-static uint32 add_cc (uint32 psr, int32 operand1, int32 operand2,
- int32 result);
-static void log_cc (int32 result, struct pstate *sregs);
-static int fpexec (uint32 op3, uint32 rd, uint32 rs1, uint32 rs2,
+static uint32_t sub_cc (uint32_t psr, int32_t operand1, int32_t operand2,
+ int32_t result);
+static uint32_t add_cc (uint32_t psr, int32_t operand1, int32_t operand2,
+ int32_t result);
+static void log_cc (int32_t result, struct pstate *sregs);
+static int fpexec (uint32_t op3, uint32_t rd, uint32_t rs1, uint32_t rs2,
struct pstate *sregs);
-static int chk_asi (struct pstate *sregs, uint32 *asi, uint32 op3);
+static int chk_asi (struct pstate *sregs, uint32_t *asi, uint32_t op3);
extern struct estate ebase;
-extern int32 nfp,ift;
+extern int32_t nfp,ift;
#ifdef ERRINJ
-extern uint32 errtt, errftt;
+extern uint32_t errtt, errftt;
#endif
-static uint32
-sub_cc(uint32 psr, int32 operand1, int32 operand2, int32 result)
+static uint32_t
+sub_cc(uint32_t psr, int32_t operand1, int32_t operand2, int32_t result)
{
psr = ((psr & ~PSR_N) | ((result >> 8) & PSR_N));
if (result)
return psr;
}
-uint32
-add_cc(uint32 psr, int32 operand1, int32 operand2, int32 result)
+uint32_t
+add_cc(uint32_t psr, int32_t operand1, int32_t operand2, int32_t result)
{
psr = ((psr & ~PSR_N) | ((result >> 8) & PSR_N));
if (result)
}
static void
-log_cc(int32 result, struct pstate *sregs)
+log_cc(int32_t result, struct pstate *sregs)
{
sregs->psr &= ~(PSR_CC); /* Zero CC bits */
sregs->psr = (sregs->psr | ((result >> 8) & PSR_N));
/* Add two unsigned 32-bit integers, and calculate the carry out. */
-static uint32
-add32 (uint32 n1, uint32 n2, int *carry)
+static uint32_t
+add32 (uint32_t n1, uint32_t n2, int *carry)
{
- uint32 result = n1 + n2;
+ uint32_t result = n1 + n2;
*carry = result < n1 || result < n2;
return result;
/* Multiply two 32-bit integers. */
static void
-mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
+mul64 (uint32_t n1, uint32_t n2, uint32_t *result_hi, uint32_t *result_lo, int msigned)
{
- uint32 lo, mid1, mid2, hi, reg_lo, reg_hi;
+ uint32_t lo, mid1, mid2, hi, reg_lo, reg_hi;
int carry;
int sign = 0;
that the host compiler supports long long operations. */
static void
-div64 (uint32 n1_hi, uint32 n1_low, uint32 n2, uint32 *result, int msigned)
+div64 (uint32_t n1_hi, uint32_t n1_low, uint32_t n2, uint32_t *result, int msigned)
{
- uint64 n1;
+ uint64_t n1;
- n1 = ((uint64) n1_hi) << 32;
- n1 |= ((uint64) n1_low) & 0xffffffff;
+ n1 = ((uint64_t) n1_hi) << 32;
+ n1 |= ((uint64_t) n1_low) & 0xffffffff;
if (msigned)
{
- int64 n1_s = (int64) n1;
- int32 n2_s = (int32) n2;
+ int64_t n1_s = (int64_t) n1;
+ int32_t n2_s = (int32_t) n2;
n1_s = n1_s / n2_s;
- n1 = (uint64) n1_s;
+ n1 = (uint64_t) n1_s;
}
else
n1 = n1 / n2;
- *result = (uint32) (n1 & 0xffffffff);
+ *result = (uint32_t) (n1 & 0xffffffff);
}
static int
-extract_short (uint32 data, uint32 address)
+extract_short (uint32_t data, uint32_t address)
{
return ((data >> ((2 - (address & 2)) * 8)) & 0xffff);
}
static int
-extract_short_signed (uint32 data, uint32 address)
+extract_short_signed (uint32_t data, uint32_t address)
{
- uint32 tmp = ((data >> ((2 - (address & 2)) * 8)) & 0xffff);
+ uint32_t tmp = ((data >> ((2 - (address & 2)) * 8)) & 0xffff);
if (tmp & 0x8000)
tmp |= 0xffff0000;
return tmp;
}
static int
-extract_byte (uint32 data, uint32 address)
+extract_byte (uint32_t data, uint32_t address)
{
return ((data >> ((3 - (address & 3)) * 8)) & 0xff);
}
static int
-extract_byte_signed (uint32 data, uint32 address)
+extract_byte_signed (uint32_t data, uint32_t address)
{
- uint32 tmp = ((data >> ((3 - (address & 3)) * 8)) & 0xff);
+ uint32_t tmp = ((data >> ((3 - (address & 3)) * 8)) & 0xff);
if (tmp & 0x80)
tmp |= 0xffffff00;
return tmp;
dispatch_instruction(struct pstate *sregs)
{
- uint32 cwp, op, op2, op3, asi, rd, cond, rs1,
+ uint32_t cwp, op, op2, op3, asi, rd, cond, rs1,
rs2;
- uint32 ldep, icc, data, *rdd;
- int32 operand1, operand2, result, eicc,
+ uint32_t ldep, icc, data, *rdd;
+ int32_t operand1, operand2, result, eicc,
new_cwp;
- int32 pc, npc, address, ws, mexc, fcc;
- uint32 ddata[2];
+ int32_t pc, npc, address, ws, mexc, fcc;
+ uint32_t ddata[2];
sregs->ninst++;
cwp = ((sregs->psr & PSR_CWP) << 4);
case DIVScc:
{
int sign;
- uint32 result, remainder;
+ uint32_t result, remainder;
int c0, y31;
if (!sparclite) {
even in cases where the divisor is subtracted
from the remainder. FIXME: get the true story
from Fujitsu. */
- c0 = result < (uint32) remainder
- || result < (uint32) operand2;
+ c0 = result < (uint32_t) remainder
+ || result < (uint32_t) operand2;
if (result & 0x80000000)
sregs->psr |= PSR_N;
break;
case SMULCC:
{
- uint32 result;
+ uint32_t result;
mul64 (rs1, operand2, &sregs->y, &result, 1);
break;
case UMULCC:
{
- uint32 result;
+ uint32_t result;
mul64 (rs1, operand2, &sregs->y, &result, 0);
break;
case SDIVCC:
{
- uint32 result;
+ uint32_t result;
if (sparclite) {
sregs->trap = TRAP_UNIMP;
break;
case UDIVCC:
{
- uint32 result;
+ uint32_t result;
if (sparclite) {
sregs->trap = TRAP_UNIMP;
case SCAN:
{
- uint32 result, mask;
+ uint32_t result, mask;
int i;
if (!sparclite) {
if (sregs->frd == rd)
sregs->fhold += (sregs->ftime - ebase.simtime);
}
- mexc = memory_write(asi, address, (uint32 *)&sregs->fsi[rd], 2, &ws);
+ mexc = memory_write(asi, address, (uint32_t *)&sregs->fsi[rd], 2, &ws);
sregs->hold += ws;
if (mexc) {
sregs->trap = TRAP_DEXC;
if ((sregs->frd == rd) || (sregs->frd + 1 == rd))
sregs->fhold += (sregs->ftime - ebase.simtime);
}
- mexc = memory_write(asi, address, (uint32 *)&sregs->fsi[rd], 3, &ws);
+ mexc = memory_write(asi, address, (uint32_t *)&sregs->fsi[rd], 3, &ws);
sregs->hold += ws;
sregs->icnt = T_STD;
#ifdef STAT
static int
-fpexec(uint32 op3, uint32 rd, uint32 rs1, uint32 rs2, struct pstate *sregs)
+fpexec(uint32_t op3, uint32_t rd, uint32_t rs1, uint32_t rs2, struct pstate *sregs)
{
- uint32 opf, tem, accex;
- int32 fcc;
- uint32 ldadj;
+ uint32_t opf, tem, accex;
+ int32_t fcc;
+ uint32_t ldadj;
if (sregs->fpstate == FP_EXC_MODE) {
sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_SEQ_ERR;
}
static int
-chk_asi(struct pstate *sregs, uint32 *asi, uint32 op3)
+chk_asi(struct pstate *sregs, uint32_t *asi, uint32_t op3)
{
if (!(sregs->psr & PSR_S)) {
sregs->trap = TRAP_PRIVI;
int
execute_trap(struct pstate *sregs)
{
- int32 cwp;
+ int32_t cwp;
if (sregs->trap == 256) {
sregs->pc = 0;
sregs->g[0] = 0;
#ifdef HOST_LITTLE_ENDIAN
sregs->fdp = (float32 *) sregs->fd;
- sregs->fsi = (int32 *) sregs->fs;
+ sregs->fsi = (int32_t *) sregs->fs;
#else
sregs->fs = (float32 *) sregs->fd;
- sregs->fsi = (int32 *) sregs->fd;
+ sregs->fsi = (int32_t *) sregs->fd;
#endif
sregs->fsr = 0;
sregs->fpu_pres = !nfp;
/* How to map SPARC FSR onto the host */
void
-set_fsr(uint32 fsr)
+set_fsr(uint32_t fsr)
{
int fround;
char uart_dev1[128] = "";
char uart_dev2[128] = "";
extern int ext_irl;
-uint32 last_load_addr = 0;
+uint32_t last_load_addr = 0;
#ifdef ERRINJ
-uint32 errcnt = 0;
-uint32 errper = 0;
-uint32 errtt = 0;
-uint32 errftt = 0;
-uint32 errmec = 0;
+uint32_t errcnt = 0;
+uint32_t errper = 0;
+uint32_t errtt = 0;
+uint32_t errftt = 0;
+uint32_t errmec = 0;
#endif
/* Forward declarations */
static int batch (struct pstate *sregs, char *fname);
-static void set_rega (struct pstate *sregs, char *reg, uint32 rval);
+static void set_rega (struct pstate *sregs, char *reg, uint32_t rval);
static void disp_reg (struct pstate *sregs, char *reg);
-static uint32 limcalc (float32 freq);
-static void int_handler (int32 sig);
+static uint32_t limcalc (float32 freq);
+static void int_handler (int32_t sig);
static void init_event (void);
static int disp_fpu (struct pstate *sregs);
static void disp_regs (struct pstate *sregs, int cwp);
static void disp_ctrl (struct pstate *sregs);
-static void disp_mem (uint32 addr, uint32 len);
+static void disp_mem (uint32_t addr, uint32_t len);
static int
batch(struct pstate *sregs, char *fname)
}
void
-set_regi(struct pstate *sregs, int32 reg, uint32 rval)
+set_regi(struct pstate *sregs, int32_t reg, uint32_t rval)
{
- uint32 cwp;
+ uint32_t cwp;
cwp = ((sregs->psr & 0x7) << 4);
if ((reg > 0) && (reg < 8)) {
}
void
-get_regi(struct pstate * sregs, int32 reg, unsigned char *buf)
+get_regi(struct pstate * sregs, int32_t reg, unsigned char *buf)
{
- uint32 cwp;
- uint32 rval = 0;
+ uint32_t cwp;
+ uint32_t rval = 0;
cwp = ((sregs->psr & 0x7) << 4);
if ((reg >= 0) && (reg < 8)) {
static void
-set_rega(struct pstate *sregs, char *reg, uint32 rval)
+set_rega(struct pstate *sregs, char *reg, uint32_t rval)
{
- uint32 cwp;
- int32 err = 0;
+ uint32_t cwp;
+ int32_t err = 0;
cwp = ((sregs->psr & 0x7) << 4);
if (strcmp(reg, "psr") == 0)
#endif
-static uint32
+static uint32_t
limcalc (float32 freq)
{
- uint32 unit, lim;
+ uint32_t unit, lim;
double flim;
char *cmd1, *cmd2;
flim = (double) lim * (double) unit * (double) freq +
(double) ebase.simtime;
if ((flim > ebase.simtime) && (flim < 4294967296.0)) {
- lim = (uint32) flim;
+ lim = (uint32_t) flim;
} else {
printf("error in expression\n");
lim = -1;
exec_cmd(struct pstate *sregs, const char *cmd)
{
char *cmd1, *cmd2;
- int32 stat;
- uint32 len, i, clen, j;
- static uint32 daddr = 0;
+ int32_t stat;
+ uint32_t len, i, clen, j;
+ static uint32_t daddr = 0;
char *cmdsave, *cmdsave2 = NULL;
stat = OK;
sim_halt();
} else if (strncmp(cmd1, "tlimit", clen) == 0) {
sregs->tlimit = limcalc(sregs->freq);
- if (sregs->tlimit != (uint32) -1)
- printf("simulation limit = %u (%.3f ms)\n",(uint32) sregs->tlimit,
+ if (sregs->tlimit != (uint32_t) -1)
+ printf("simulation limit = %u (%.3f ms)\n",(uint32_t) sregs->tlimit,
sregs->tlimit / sregs->freq / 1000);
} else if (strncmp(cmd1, "tra", clen) == 0) {
if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
void
show_stat(struct pstate *sregs)
{
- uint32 iinst;
- uint32 stime;
+ uint32_t iinst;
+ uint32_t stime;
if (sregs->tottime == 0.0)
sregs->tottime += 1E-6;
}
static void
-int_handler(int32 sig)
+int_handler(int32_t sig)
{
if (sig != 2)
printf("\n\n Signal handler error (%d)\n\n", sig);
}
}
-static void print_insn_sparc_sis(uint32 addr, struct disassemble_info *info)
+static void print_insn_sparc_sis(uint32_t addr, struct disassemble_info *info)
{
unsigned char i[4];
disp_ctrl(struct pstate *sregs)
{
- uint32 i;
+ uint32_t i;
printf("\n psr: %08X wim: %08X tbr: %08X y: %08X\n",
sregs->psr, sregs->wim, sregs->tbr, sregs->y);
}
static void
-disp_mem(uint32 addr, uint32 len)
+disp_mem(uint32_t addr, uint32_t len)
{
- uint32 i;
+ uint32_t i;
union {
unsigned char u8[4];
- uint32 u32;
+ uint32_t u32;
} data;
- uint32 mem[4], j;
+ uint32_t mem[4], j;
char *p;
for (i = addr & ~3; i < ((addr + len) & ~3); i += 16) {
}
void
-dis_mem(uint32 addr, uint32 len, struct disassemble_info *info)
+dis_mem(uint32_t addr, uint32_t len, struct disassemble_info *info)
{
- uint32 i;
+ uint32_t i;
union {
unsigned char u8[4];
- uint32 u32;
+ uint32_t u32;
} data;
for (i = addr & -3; i < ((addr & -3) + (len << 2)); i += 4) {
/* Add event to event queue */
void
-event(void (*cfunc) (), int32 arg, uint64 delta)
+event(void (*cfunc) (), int32_t arg, uint64_t delta)
{
struct evcell *ev1, *evins;
void
init_event(void)
{
- int32 i;
+ int32_t i;
ebase.eq.nxt = NULL;
ebase.freeq = evbuf;
}
void
-set_int(int32 level, void (*callback) (), int32 arg)
+set_int(int32_t level, void (*callback) (), int32_t arg)
{
irqarr[level & 0x0f].callback = callback;
irqarr[level & 0x0f].arg = arg;
struct evcell *evrem;
void (*cfunc) ();
- uint32 arg;
- uint64 endtime;
+ uint32_t arg;
+ uint64_t endtime;
#ifdef STAT
sregs->fholdt += sregs->fhold;
}
-uint32
+uint32_t
now(void)
{
return ebase.simtime;
{
struct evcell *evrem;
void (*cfunc) ();
- int32 arg;
- uint64 endtime;
+ int32_t arg;
+ uint64_t endtime;
if (ebase.eq.nxt == NULL)
printf("Warning: event queue empty - power-down mode not entered\n");
int
check_bpt(struct pstate *sregs)
{
- int32 i;
+ int32_t i;
if ((sregs->bphit) || (sregs->annul))
return 0;
- for (i = 0; i < (int32) sregs->bptnum; i++) {
+ for (i = 0; i < (int32_t) sregs->bptnum; i++) {
if (sregs->pc == sregs->bpts[i])
return BPT_HIT;
}
host_callback *sim_callback;
int
-run_sim(struct pstate *sregs, uint64 icount, int dis)
+run_sim(struct pstate *sregs, uint64_t icount, int dis)
{
int mexc, irq;
for (win = invwin; ; win = (win - 1) & PSR_CWP)
{
- uint32 sp;
+ uint32_t sp;
int i;
sp = sregs.r[(win * 16 + 14) & 0x7f];
#if 1
if (sis_verbose > 2) {
- uint32 fp = sregs.r[(win * 16 + 30) & 0x7f];
+ uint32_t fp = sregs.r[(win * 16 + 30) & 0x7f];
printf("flush_window: win %d, sp %x, fp %x\n", win, sp, fp);
}
#endif
extern int dumbio;
extern char uart_dev1[];
extern char uart_dev2[];
-extern uint32 last_load_addr;
+extern uint32_t last_load_addr;
#ifdef ERA
extern int era;
#endif
int
-run_sim(struct pstate *sregs, uint64 icount, int dis)
+run_sim(struct pstate *sregs, uint64_t icount, int dis)
{
int irq, mexc, deb;
/* type definitions */
-typedef short int int16; /* 16-bit signed int */
-typedef unsigned short int uint16; /* 16-bit unsigned int */
-typedef int int32; /* 32-bit signed int */
-typedef unsigned int uint32; /* 32-bit unsigned int */
typedef float float32; /* 32-bit float */
typedef double float64; /* 64-bit float */
-typedef uint64_t uint64; /* 64-bit unsigned int */
-typedef int64_t int64; /* 64-bit signed int */
-
struct pstate {
float64 fd[16]; /* FPU registers */
#else
float32 *fs;
#endif
- int32 *fsi;
- uint32 fsr;
- int32 fpstate;
- uint32 fpq[FPUQN * 2];
- uint32 fpqn;
- uint32 ftime;
- uint32 flrd;
- uint32 frd;
- uint32 frs1;
- uint32 frs2;
- uint32 fpu_pres; /* FPU present (0 = No, 1 = Yes) */
-
- uint32 psr; /* IU registers */
- uint32 tbr;
- uint32 wim;
- uint32 g[8];
- uint32 r[128];
- uint32 y;
- uint32 asr17; /* Single vector trapping */
- uint32 pc, npc;
-
-
- uint32 trap; /* Current trap type */
- uint32 annul; /* Instruction annul */
- uint32 data; /* Loaded data */
- uint32 inst; /* Current instruction */
- uint32 asi; /* Current ASI */
- uint32 err_mode; /* IU error mode */
- uint32 breakpoint;
- uint32 bptnum;
- uint32 bphit;
- uint32 bpts[BPT_MAX]; /* Breakpoints */
-
- uint32 ltime; /* Load interlock time */
- uint32 hold; /* IU hold cycles in current inst */
- uint32 fhold; /* FPU hold cycles in current inst */
- uint32 icnt; /* Instruction cycles in curr inst */
-
- uint32 histlen; /* Trace history management */
- uint32 histind;
+ int32_t *fsi;
+ uint32_t fsr;
+ int32_t fpstate;
+ uint32_t fpq[FPUQN * 2];
+ uint32_t fpqn;
+ uint32_t ftime;
+ uint32_t flrd;
+ uint32_t frd;
+ uint32_t frs1;
+ uint32_t frs2;
+ uint32_t fpu_pres; /* FPU present (0 = No, 1 = Yes) */
+
+ uint32_t psr; /* IU registers */
+ uint32_t tbr;
+ uint32_t wim;
+ uint32_t g[8];
+ uint32_t r[128];
+ uint32_t y;
+ uint32_t asr17; /* Single vector trapping */
+ uint32_t pc, npc;
+
+
+ uint32_t trap; /* Current trap type */
+ uint32_t annul; /* Instruction annul */
+ uint32_t data; /* Loaded data */
+ uint32_t inst; /* Current instruction */
+ uint32_t asi; /* Current ASI */
+ uint32_t err_mode; /* IU error mode */
+ uint32_t breakpoint;
+ uint32_t bptnum;
+ uint32_t bphit;
+ uint32_t bpts[BPT_MAX]; /* Breakpoints */
+
+ uint32_t ltime; /* Load interlock time */
+ uint32_t hold; /* IU hold cycles in current inst */
+ uint32_t fhold; /* FPU hold cycles in current inst */
+ uint32_t icnt; /* Instruction cycles in curr inst */
+
+ uint32_t histlen; /* Trace history management */
+ uint32_t histind;
struct histype *histbuf;
float32 freq; /* Simulated processor frequency */
double tottime;
- uint64 ninst;
- uint64 fholdt;
- uint64 holdt;
- uint64 icntt;
- uint64 finst;
- uint64 simstart;
+ uint64_t ninst;
+ uint64_t fholdt;
+ uint64_t holdt;
+ uint64_t icntt;
+ uint64_t finst;
+ uint64_t simstart;
double starttime;
- uint64 tlimit; /* Simulation time limit */
- uint64 pwdtime; /* Cycles in power-down mode */
- uint64 nstore; /* Number of load instructions */
- uint64 nload; /* Number of store instructions */
- uint64 nannul; /* Number of annuled instructions */
- uint64 nbranch; /* Number of branch instructions */
- uint32 ildreg; /* Destination of last load instruction */
- uint64 ildtime; /* Last time point for load dependency */
+ uint64_t tlimit; /* Simulation time limit */
+ uint64_t pwdtime; /* Cycles in power-down mode */
+ uint64_t nstore; /* Number of load instructions */
+ uint64_t nload; /* Number of store instructions */
+ uint64_t nannul; /* Number of annuled instructions */
+ uint64_t nbranch; /* Number of branch instructions */
+ uint32_t ildreg; /* Destination of last load instruction */
+ uint64_t ildtime; /* Last time point for load dependency */
int rett_err; /* IU in jmpl/restore error state (Rev.0) */
int jmpltime;
struct evcell {
void (*cfunc) ();
- int32 arg;
- uint64 time;
+ int32_t arg;
+ uint64_t time;
struct evcell *nxt;
};
struct estate {
struct evcell eq;
struct evcell *freeq;
- uint64 simtime;
+ uint64_t simtime;
};
struct irqcell {
void (*callback) ();
- int32 arg;
+ int32_t arg;
};
/* erc32.c */
extern void init_sim (void);
extern void reset (void);
-extern void error_mode (uint32 pc);
+extern void error_mode (uint32_t pc);
extern void sim_halt (void);
extern void exit_sim (void);
extern void init_stdio (void);
extern void restore_stdio (void);
-extern int memory_iread (uint32 addr, uint32 *data, uint32 *ws);
-extern int memory_read (int32 asi, uint32 addr, void *data,
- int32 sz, int32 *ws);
-extern int memory_write (int32 asi, uint32 addr, uint32 *data,
- int32 sz, int32 *ws);
-extern int sis_memory_write (uint32 addr,
- const void *data, uint32 length);
-extern int sis_memory_read (uint32 addr, void *data,
- uint32 length);
+extern int memory_iread (uint32_t addr, uint32_t *data, uint32_t *ws);
+extern int memory_read (int32_t asi, uint32_t addr, void *data,
+ int32_t sz, int32_t *ws);
+extern int memory_write (int32_t asi, uint32_t addr, uint32_t *data,
+ int32_t sz, int32_t *ws);
+extern int sis_memory_write (uint32_t addr,
+ const void *data, uint32_t length);
+extern int sis_memory_read (uint32_t addr, void *data,
+ uint32_t length);
extern void boot_init (void);
/* func.c */
extern struct pstate sregs;
-extern void set_regi (struct pstate *sregs, int32 reg,
- uint32 rval);
-extern void get_regi (struct pstate *sregs, int32 reg, unsigned char *buf);
+extern void set_regi (struct pstate *sregs, int32_t reg,
+ uint32_t rval);
+extern void get_regi (struct pstate *sregs, int32_t reg, unsigned char *buf);
extern int exec_cmd (struct pstate *sregs, const char *cmd);
extern void reset_stat (struct pstate *sregs);
extern void show_stat (struct pstate *sregs);
extern void init_signals (void);
struct disassemble_info;
-extern void dis_mem (uint32 addr, uint32 len,
+extern void dis_mem (uint32_t addr, uint32_t len,
struct disassemble_info *info);
-extern void event (void (*cfunc) (), int32 arg, uint64 delta);
-extern void set_int (int32 level, void (*callback) (), int32 arg);
+extern void event (void (*cfunc) (), int32_t arg, uint64_t delta);
+extern void set_int (int32_t level, void (*callback) (), int32_t arg);
extern void advance_time (struct pstate *sregs);
-extern uint32 now (void);
+extern uint32_t now (void);
extern int wait_for_irq (void);
extern int check_bpt (struct pstate *sregs);
extern void reset_all (void);
/* interf.c */
extern int run_sim (struct pstate *sregs,
- uint64 icount, int dis);
+ uint64_t icount, int dis);
/* float.c */
extern int get_accex (void);
extern void clear_accex (void);
-extern void set_fsr (uint32 fsr);
+extern void set_fsr (uint32_t fsr);
/* help.c */
extern void usage (void);
projects / binutils-gdb.git / commitdiff