proc_clean: fix order of switch insertion.

Fixes #1268.

diff --git a/Makefile b/Makefile
index 16341a2683bb0161d05aad0fc245fc8a25ec4577..382f79546dcef01c576b4c528df0b5c5b08a0e45 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -695,6 +695,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
        +cd tests/various && bash run-test.sh
        +cd tests/sat && bash run-test.sh
        +cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
+       +cd tests/proc && bash run-test.sh
        +cd tests/opt && bash run-test.sh
        +cd tests/aiger && bash run-test.sh $(ABCOPT)
        +cd tests/arch && bash run-test.sh

diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 97f4c6573f4d9cabfc96a0f9df9108f5aef4d5b4..114c6ab039356ff6c11e95acb8e50806024516cb 100644 (file)
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -69,8 +69,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
                did_something = true;
                for (auto &action : sw->cases[0]->actions)
                        parent->actions.push_back(action);
-               for (auto sw2 : sw->cases[0]->switches)
-                       parent->switches.push_back(sw2);
+               parent->switches.insert(parent->switches.begin(), sw->cases[0]->switches.begin(), sw->cases[0]->switches.end());
                sw->cases[0]->switches.clear();
                delete sw->cases[0];
                sw->cases.clear();

diff --git a/tests/proc/.gitignore b/tests/proc/.gitignore
new file mode 100644 (file)
index 0000000..397b4a7
--- /dev/null
+++ b/tests/proc/.gitignore
@@ -0,0 +1 @@
+*.log

diff --git a/tests/proc/bug_1268.v b/tests/proc/bug_1268.v
new file mode 100644 (file)
index 0000000..698ac93
--- /dev/null
+++ b/tests/proc/bug_1268.v
@@ -0,0 +1,23 @@
+module gold (input clock, ctrl, din, output reg dout);
+       always @(posedge clock) begin
+               if (1'b1) begin
+                       if (1'b0) begin end else begin
+                               dout <= 0;
+                       end
+                       if (ctrl)
+                               dout <= din;
+               end
+       end
+endmodule
+
+module gate (input clock, ctrl, din, output reg dout);
+       always @(posedge clock) begin
+               if (1'b1) begin
+                       if (1'b0) begin end else begin
+                               dout <= 0;
+                       end
+               end
+               if (ctrl)
+                       dout <= din;
+       end
+endmodule

diff --git a/tests/proc/bug_1268.ys b/tests/proc/bug_1268.ys
new file mode 100644 (file)
index 0000000..b73e944
--- /dev/null
+++ b/tests/proc/bug_1268.ys
@@ -0,0 +1,5 @@
+read_verilog bug_1268.v
+proc
+equiv_make gold gate equiv
+equiv_induct
+equiv_status -assert

diff --git a/tests/proc/run-test.sh b/tests/proc/run-test.sh
new file mode 100755 (executable)
index 0000000..44ce7e6
--- /dev/null
+++ b/tests/proc/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done