from nmigen import *
-from nmigen.back import rtlil, verilog
+from nmigen.cli import main
class ALU:
return m.lower(platform)
-alu = ALU(width=16)
-frag = alu.get_fragment(platform=None)
-# print(rtlil.convert(frag, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co]))
-print(verilog.convert(frag, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co]))
+if __name__ == "__main__":
+ alu = ALU(width=16)
+ main(alu, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co])
from nmigen import *
-from nmigen.back import rtlil, verilog
+from nmigen.cli import main
class Adder:
return m.lower(platform)
-alu = ALU(width=16)
-frag = alu.get_fragment(platform=None)
-# print(rtlil.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))
-print(verilog.convert(frag, ports=[alu.op, alu.a, alu.b, alu.o]))
+if __name__ == "__main__":
+ alu = ALU(width=16)
+ main(alu, ports=[alu.op, alu.a, alu.b, alu.o])
from nmigen import *
-from nmigen.back import rtlil, verilog
+from nmigen.cli import main
class ClockDivisor:
return m.lower(platform)
-ctr = ClockDivisor(factor=16)
-frag = ctr.get_fragment(platform=None)
-frag.add_domains(ClockDomain("sync", async_reset=True))
-# print(rtlil.convert(frag, ports=[ctr.o]))
-print(verilog.convert(frag, ports=[ctr.o]))
+if __name__ == "__main__":
+ ctr = ClockDivisor(factor=16)
+ frag = ctr.get_fragment(platform=None)
+ frag.add_domains(ClockDomain("sync", async_reset=True))
+ main(frag, ports=[ctr.o])
from nmigen import *
-from nmigen.back import rtlil, verilog
+from nmigen.cli import main
i, o = Signal(name="i"), Signal(name="o")
m = Module()
m.submodules += MultiReg(i, o)
-frag = m.lower(platform=None)
-# print(rtlil.convert(frag, ports=[i, o]))
-print(verilog.convert(frag, ports=[i, o]))
+
+if __name__ == "__main__":
+ main(m.lower(platform=None), ports=[i, o])
from nmigen import *
-from nmigen.back import rtlil, verilog, pysim
+from nmigen.cli import main, pysim
class Counter:
return m.lower(platform)
-ctr = Counter(width=16)
-frag = ctr.get_fragment(platform=None)
-
-# print(rtlil.convert(frag, ports=[ctr.o]))
-print(verilog.convert(frag, ports=[ctr.o]))
-
-with pysim.Simulator(frag,
- vcd_file=open("ctr.vcd", "w")) as sim:
- sim.add_clock(1e-6)
- sim.run_until(100e-6, run_passive=True)
+ctr = Counter(width=16)
+if __name__ == "__main__":
+ main(ctr, ports=[ctr.o])
from types import SimpleNamespace
from nmigen import *
-from nmigen.back import rtlil, verilog, pysim
+from nmigen.cli import main
class GPIO:
return m.lower(platform)
-# TODO: use Record
-bus = SimpleNamespace(
- adr=Signal(max=8),
- dat_r=Signal(),
- dat_w=Signal(),
- we=Signal()
-)
-pins = Signal(8)
-gpio = GPIO(Array(pins), bus)
-frag = gpio.get_fragment(platform=None)
-
-# print(rtlil.convert(frag, ports=[pins, bus.adr, bus.dat_r, bus.dat_w, bus.we]))
-print(verilog.convert(frag, ports=[pins, bus.adr, bus.dat_r, bus.dat_w, bus.we]))
+if __name__ == "__main__":
+ # TODO: use Record
+ bus = SimpleNamespace(
+ adr =Signal(name="adr", max=8),
+ dat_r=Signal(name="dat_r"),
+ dat_w=Signal(name="dat_w"),
+ we =Signal(name="we"),
+ )
+ pins = Signal(8)
+ gpio = GPIO(Array(pins), bus)
+ main(gpio, ports=[pins, bus.adr, bus.dat_r, bus.dat_w, bus.we])
from nmigen import *
-from nmigen.back import rtlil, verilog
+from nmigen.cli import main
class System:
def get_fragment(self, platform):
m = Module()
- m.submodules += Instance("CPU",
+ m.submodules.cpu = Instance("CPU",
p_RESET_ADDR=0xfff0,
i_d_adr =self.adr,
i_d_dat_r=self.dat_r,
return m.lower(platform)
-sys = System()
-frag = sys.get_fragment(platform=None)
-# print(rtlil.convert(frag, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we]))
-print(verilog.convert(frag, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we]))
+if __name__ == "__main__":
+ sys = System()
+ main(sys, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we])
from nmigen import *
-from nmigen.back import rtlil, verilog
+from nmigen.cli import main
class RegisterFile:
return m.lower(platform)
-rf = RegisterFile()
-frag = rf.get_fragment(platform=None)
-# print(rtlil.convert(frag, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we]))
-print(verilog.convert(frag, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we]))
+if __name__ == "__main__":
+ rf = RegisterFile()
+ main(rf, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we])
from nmigen import *
-from nmigen.back import rtlil, verilog
+from nmigen.cli import main
class ParMux:
return m.lower(platform)
-pmux = ParMux(width=16)
-frag = pmux.get_fragment(platform=None)
-# print(rtlil.convert(frag, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o]))
-print(verilog.convert(frag, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o]))
+if __name__ == "__main__":
+ pmux = ParMux(width=16)
+ main(pmux, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o])
--- /dev/null
+import argparse
+
+from .back import rtlil, verilog, pysim
+
+
+__all__ = ["main"]
+
+
+def main_parser(parser=None):
+ if parser is None:
+ parser = argparse.ArgumentParser()
+
+ p_action = parser.add_subparsers(dest="action")
+
+ p_generate = p_action.add_parser("generate",
+ help="generate RTLIL or Verilog from the design")
+ p_generate.add_argument("-t", "--type", dest="generate_type",
+ metavar="LANGUAGE", choices=["il", "v"], default="v",
+ help="generate LANGUAGE (il for RTLIL, v for Verilog; default: %(default)s)")
+ p_generate.add_argument("generate_file",
+ metavar="FILE", type=argparse.FileType("w"), nargs="?",
+ help="write generated code to FILE")
+
+ p_simulate = p_action.add_parser(
+ "simulate", help="simulate the design")
+ p_simulate.add_argument("-v", "--vcd-file",
+ metavar="VCD-FILE", type=argparse.FileType("w"),
+ help="write execution trace to VCD-FILE")
+ p_simulate.add_argument("-w", "--gtkw-file",
+ metavar="GTKW-FILE", type=argparse.FileType("w"),
+ help="write GTKWave configuration to GTKW-FILE")
+ p_simulate.add_argument("-p", "--period", dest="sync_period",
+ metavar="TIME", type=float, default=1e-6,
+ help="set 'sync' clock domain period to TIME (default: %(default)s)")
+ p_simulate.add_argument("-c", "--clocks", dest="sync_clocks",
+ metavar="COUNT", type=int, required=True,
+ help="simulate for COUNT 'sync' clock periods")
+
+ return parser
+
+
+def main_runner(args, design, platform=None, name="top", ports=()):
+ if args.action == "generate":
+ fragment = design.get_fragment(platform=platform)
+ if args.generate_type == "il":
+ output = rtlil.convert(fragment, name=name, ports=ports)
+ if args.generate_type == "v":
+ output = verilog.convert(fragment, name=name, ports=ports)
+ if args.generate_file:
+ args.generate_file.write(output)
+ else:
+ print(output)
+
+ if args.action == "simulate":
+ fragment = design.get_fragment(platform=platform)
+ with pysim.Simulator(fragment,
+ vcd_file=args.vcd_file,
+ gtkw_file=args.gtkw_file,
+ traces=ports) as sim:
+ sim.add_clock(args.sync_period)
+ sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)
+
+
+def main(*args, **kwargs):
+ main_runner(main_parser().parse_args(), *args, **kwargs)
projects / nmigen.git / commitdiff