Change how to specify flops to ABC again

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ba0e36ce153ce8139a8064ad4fc685fefc0c4549..53b6ff97ab2132699b6dc257880b7b17505fd140 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -273,17 +273,27 @@ struct XAigerWriter
                                toposort.node(cell->name);
 
                                auto r = flop_data.insert(std::make_pair(cell->type, std::make_pair(IdString(), IdString())));
-                               if (r.second) {
-                                       auto it = inst_module->attributes.find("\\abc_flop");
-                                       if (it != inst_module->attributes.end()) {
-                                               auto abc_flop = it->second.decode_string();
-                                               auto tokens = split_tokens(abc_flop, ",");
-                                               if (tokens.size() != 4)
-                                                       log_error("'abc_flop' attribute on module '%s' does not contain exactly four comma-separated tokens.\n", log_id(cell->type));
-                                               auto abc_flop_d = RTLIL::escape_id(tokens[1]);
-                                               auto abc_flop_q = RTLIL::escape_id(tokens[2]);
-                                               r.first->second = std::make_pair(abc_flop_d, abc_flop_q);
+                               if (r.second && inst_module->attributes.count("\\abc_flop")) {
+                                       IdString abc_flop_d, abc_flop_q;
+                                       for (auto port_name : inst_module->ports) {
+                                               auto wire = inst_module->wire(port_name);
+                                               log_assert(wire);
+                                               if (wire->attributes.count("\\abc_flop_d")) {
+                                                       if (abc_flop_d != IdString())
+                                                               log_error("More than one port has the 'abc_flop_d' attribute set on module '%s'.\n", log_id(cell->type));
+                                                       abc_flop_d = port_name;
+                                               }
+                                               if (wire->attributes.count("\\abc_flop_q")) {
+                                                       if (abc_flop_q != IdString())
+                                                               log_error("More than one port has the 'abc_flop_q' attribute set on module '%s'.\n", log_id(cell->type));
+                                                       abc_flop_q = port_name;
+                                               }
                                        }
+                                       if (abc_flop_d == IdString())
+                                               log_error("'abc_flop_d' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
+                                       if (abc_flop_q == IdString())
+                                               log_error("'abc_flop_q' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
+                                       r.first->second = std::make_pair(abc_flop_d, abc_flop_q);
                                }
 
                                auto abc_flop_d = r.first->second.first;

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 35b7f6a97e38915425068f86281f780caeeb19ab..11c5e35700183b594015e585957b9c5c95fc1d57 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -742,27 +742,23 @@ void AigerReader::parse_aiger_binary()
 void AigerReader::post_process()
 {
        pool<IdString> seen_boxes;
-       dict<IdString, std::pair<RTLIL::Module*,IdString>> flop_data;
+       dict<IdString, RTLIL::Module*> flop_data;
        unsigned ci_count = 0, co_count = 0, flop_count = 0;
        for (auto cell : boxes) {
                RTLIL::Module* box_module = design->module(cell->type);
                log_assert(box_module);
 
                RTLIL::Module* flop_module = nullptr;
-               RTLIL::IdString flop_past_q;
+               const RTLIL::IdString flop_past_q = RTLIL::escape_id("\\$pastQ");
                if (seen_boxes.insert(cell->type).second) {
                        auto it = box_module->attributes.find("\\abc_flop");
                        if (it != box_module->attributes.end()) {
                                log_assert(flop_count < flopNum);
                                auto abc_flop = it->second.decode_string();
-                               auto tokens = split_tokens(abc_flop, ",");
-                               if (tokens.size() != 4)
-                                       log_error("'abc_flop' attribute on module '%s' does not contain exactly four comma-separated tokens.\n", log_id(cell->type));
-                               flop_module = design->module(RTLIL::escape_id(tokens[0]));
+                               flop_module = design->module(RTLIL::escape_id(abc_flop));
                                if (!flop_module)
-                                       log_error("First token '%s' in 'abc_flop' attribute on module '%s' is not a valid module.\n", tokens[0].c_str(), log_id(cell->type));
-                               flop_past_q = RTLIL::escape_id(tokens[3]);
-                               flop_data[cell->type] = std::make_pair(flop_module, flop_past_q);
+                                       log_error("'abc_flop' attribute value '%s' on module '%s' is not a valid module.\n", abc_flop.c_str(), log_id(cell->type));
+                               flop_data[cell->type] = flop_module;
                        }
                        it = box_module->attributes.find("\\abc_carry");
                        if (it != box_module->attributes.end()) {
@@ -806,7 +802,7 @@ void AigerReader::post_process()
                else {
                        auto it = flop_data.find(cell->type);
                        if (it != flop_data.end())
-                               std::tie(flop_module,flop_past_q) = it->second;
+                               flop_module = it->second;
                }
 
                // NB: Assume box_module->ports are sorted alphabetically

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 1d9a25ba70c8dc973492ebfca9f94c3464715333..db63232b78e97da4747ab3909be098659a178295 100644 (file)
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -86,23 +86,35 @@ module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Q);
 //  assign Q = S ? B : A;
 endmodule
 
-(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
-module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
+(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE" *)
+module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  (* abc_flop_clk_inv *) parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 endmodule
 
-(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
-module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
+(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1" *)
+module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 endmodule
 
-(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
-module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
+(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE" *)
+module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -110,14 +122,22 @@ module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
   assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
-module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
+(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1" *)
+module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   assign Q = (CE && !CLR) ? D : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
-module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
+(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE" *)
+module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -125,8 +145,12 @@ module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
   assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
-module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
+(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1" *)
+module \$__ABC_FDPE_1 ((* abc_flop_q *)   output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   assign Q = (CE && !PRE) ? D : \$pastQ ;
 endmodule