Fixed a type in $mem model in simlib.v

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f3d652f0e06d7fbc54134e8109dff70916380802..321119e37ed1380f825a866a17b006f03b61dcf4 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1036,7 +1036,7 @@ generate
                                end
                        end
                end else
-               if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk
+               if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk
                        always @(posedge WR_CLK[i])
                                if (WR_EN[i]) begin
                                        data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];