arch-arm: Fix build errors with gcc 10.2

The "-Werror=type-limits" flag in GCC 10.2 reports these errors,
because ``imm`` in neon.isa, and ``imm`` and ``count`` in sve.isa are
unsigned, and they're used to do ``imm < 0`` and ``imm * count >= 0``
comparison.

Change-Id: I33934357f578a9fc1040a6d9c08ea929fb36eb47
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33154
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index aa67353b77b38086992d52dae57816a8d5f47914..d536d5b8d010cde004998bf58a16661c97cf9bfa 100644 (file)
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -1416,7 +1416,7 @@ let {{
         if readDest:
             readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
-        if (imm < 0 && imm >= eCount) {
+        if (imm >= eCount) {
             fault = std::make_shared<UndefinedInstruction>(machInst, false,
                                                            mnemonic);
         } else {
@@ -1468,7 +1468,7 @@ let {{
         if readDest:
             readDestCode = 'destElem = letoh(destReg.elements[i]);'
         eWalkCode += '''
-        if (imm < 0 && imm >= eCount) {
+        if (imm >= eCount) {
             fault = std::make_shared<UndefinedInstruction>(machInst, false,
                                                           mnemonic);
         } else {
@@ -1518,7 +1518,7 @@ let {{
         if readDest:
             readDestCode = 'destReg = destRegs[i];'
         eWalkCode += '''
-        if (imm < 0 && imm >= eCount) {
+        if (imm >= eCount) {
             fault = std::make_shared<UndefinedInstruction>(machInst, false,
                                                            mnemonic);
         } else {

diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 9314ba9a62581858536a2a9f4da00108739bf1cd..4e49e9294ec347760c3332bd3366372ea957027b 100644 (file)
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -4335,13 +4335,10 @@ let {{
         destElem = srcElem1 - (count * imm);
         bool negDest = (destElem < 0);
         bool negSrc = (srcElem1 < 0);
-        bool posCount = ((count * imm) >= 0);
-        if ((negDest != negSrc) && (negSrc == posCount)) {
+        if (!negDest && negSrc) {
             destElem = static_cast<%(dstType)s>(
                 (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1)
                 );
-            if (negDest)
-                destElem -= 1;
         }
     '''
     sveElemCountInst('sqdec', 'Sqdec32', 'SimdAluOp', signedTypes,
@@ -4394,13 +4391,11 @@ let {{
         destElem = srcElem1 + (count * imm);
         bool negDest = (destElem < 0);
         bool negSrc = (srcElem1 < 0);
-        bool negCount = ((count * imm) < 0);
-        if ((negDest != negSrc) && (negSrc == negCount)) {
+        if (negDest && !negSrc) {
             destElem = static_cast<%(dstType)s>(
                 (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1)
                 );
-            if (negDest)
-                destElem -= 1;
+            destElem -= 1;
         }
     '''
     sveElemCountInst('sqinc', 'Sqinc32', 'SimdAluOp', signedTypes,