radeonsi: fix signature of export intrinsic in VS epilog

The incompatible signature becomes an issue when the VS epilog gets merged
with the main vertex shader at the IR level.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 2b8c168a1f0b6e916e3c889e5e006ce5f8f6dbf7..887174257aaa72ddfe3c723036e07b43c6d26aa1 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7114,9 +7114,9 @@ static bool si_compile_vs_epilog(struct si_screen *sscreen,
                args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
                args[5] = LLVMGetParam(ctx.main_fn,
                                       VS_EPILOG_PRIMID_LOC); /* X */
-               args[6] = uint->undef; /* Y */
-               args[7] = uint->undef; /* Z */
-               args[8] = uint->undef; /* W */
+               args[6] = base->undef; /* Y */
+               args[7] = base->undef; /* Z */
+               args[8] = base->undef; /* W */
 
                lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
                                   LLVMVoidTypeInContext(base->gallivm->context),