arch,sim: Merge initCPU into the ISA System classes.

Those classes are already ISA specific, so we can just move initCPU's
contents there and take it out of utility.hh, utility.cc, and the base
System's initState.

Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 4e2420dc950531274bdb55a5243382d7ab56c3ab..3613d305c57f34a0d8b3f029f0bcd84ed54d4d1a 100644 (file)
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -61,26 +61,6 @@ getDTBPtr(T *tc)
     return tlb;
 }
 
-////////////////////////////////////////////////////////////////////////
-//
-//  Machine dependent functions
-//
-void
-initCPU(ThreadContext *tc, int cpuId)
-{
-    initIPRs(tc, cpuId);
-
-    tc->setIntReg(16, cpuId);
-    tc->setIntReg(0, cpuId);
-
-    Addr base = tc->readMiscRegNoEffect(IPR_PAL_BASE);
-    Addr offset = ResetFault().vect();
-
-    tc->pcState(base + offset);
-
-    tc->activate();
-}
-
 ////////////////////////////////////////////////////////////////////////
 //
 //

diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index ca4551f6062b5d3534a56f7f5012803d80ddc00d..f491b1159ccaae3328e472a4ef6b0dc121c0bde3 100644 (file)
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -34,6 +34,7 @@
 #include <sys/signal.h>
 
 #include "arch/alpha/ev5.hh"
+#include "arch/alpha/faults.hh"
 #include "arch/vtophys.hh"
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
@@ -108,6 +109,21 @@ AlphaSystem::initState()
     // Call the initialisation of the super class
     System::initState();
 
+    for (auto *tc: threadContexts) {
+        int cpuId = tc->contextId();
+        initIPRs(tc, cpuId);
+
+        tc->setIntReg(16, cpuId);
+        tc->setIntReg(0, cpuId);
+
+        Addr base = tc->readMiscRegNoEffect(IPR_PAL_BASE);
+        Addr offset = ResetFault().vect();
+
+        tc->pcState(base + offset);
+
+        tc->activate();
+    }
+
     // Load program sections into memory
     pal->buildImage().mask(loadAddrMask).write(physProxy);
     console->buildImage().mask(loadAddrMask).write(physProxy);

diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index a0f70a331bd83ace46b3f5c21111fa3aa443ff94..ae63f1b380841972ed097cb23b04a1c3dfb94b7d 100644 (file)
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -87,7 +87,6 @@ RoundPage(Addr addr)
 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
 
 void initIPRs(ThreadContext *tc, int cpuId);
-void initCPU(ThreadContext *tc, int cpuId);
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 

diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 5c32059f4636f7994e330913761be4bd61e66b9a..61cc5c3c929ca40509f8c26c387152290d8773f2 100644 (file)
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -44,6 +44,7 @@
 
 #include <iostream>
 
+#include "arch/arm/faults.hh"
 #include "arch/arm/semihosting.hh"
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
@@ -136,6 +137,15 @@ ArmSystem::initState()
     // Call the initialisation of the super class
     System::initState();
 
+    // Reset CP15?? What does that mean -- ali
+
+    // FPEXC.EN = 0
+
+    for (auto *tc: threadContexts) {
+        Reset().invoke(tc);
+        tc->activate();
+    }
+
     const Params* p = params();
 
     if (bootldr) {

diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 627fc5357f00ec8e7172385d07a0f21e1643ea0f..e8ca13d0efa36b8a9368bb706f2983b62d21f7d9 100644 (file)
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -52,18 +52,8 @@
 #include "mem/fs_translating_port_proxy.hh"
 #include "sim/full_system.hh"
 
-namespace ArmISA {
-
-void
-initCPU(ThreadContext *tc, int cpuId)
+namespace ArmISA
 {
-    // Reset CP15?? What does that mean -- ali
-
-    // FPEXC.EN = 0
-
-    Reset().invoke(tc);
-    tc->activate();
-}
 
 uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index d209664cb0bb6865f9bcd325fbbf881258dbdf9e..e70056d6a466b20e1502869afc8fd6924252eaae 100644 (file)
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -103,8 +103,6 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
     panic("Copy Misc. Regs Not Implemented Yet\n");
 }
 
-void initCPU(ThreadContext *tc, int cpuId);
-
 /** Send an event (SEV) to a specific PE if there isn't
  * already a pending event */
 void sendEvent(ThreadContext *tc);

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index a98b58e311681a1b2cb577aa3cc14dd0f0ff342a..fe06ca17c4bebfbe55e18defde691e1ca1cb4c85 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -217,12 +217,6 @@ isSnan(void *val_ptr, int size)
     }
 }
 
-void
-initCPU(ThreadContext *tc, int cpuId)
-{
-    tc->activate();
-}
-
 void
 copyRegs(ThreadContext *src, ThreadContext *dest)
 {

diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 67fe3a45b61cf59ea0e0d86cd801c5696e377148..3338550cc0db09edec48330bad772dca5d883d09 100644 (file)
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -93,17 +93,15 @@ inUserMode(ThreadContext *tc)
 //
 inline Addr
 TruncPage(Addr addr)
-{ return addr & ~(PageBytes - 1); }
+{
+    return addr & ~(PageBytes - 1);
+}
 
 inline Addr
 RoundPage(Addr addr)
-{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
-
-////////////////////////////////////////////////////////////////////////
-//
-// CPU Utility
-//
-void initCPU(ThreadContext *tc, int cpuId);
+{
+    return (addr + PageBytes - 1) & ~(PageBytes - 1);
+}
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);

diff --git a/src/arch/null/utility.hh b/src/arch/null/utility.hh
index 69055c706d047289bc0193ede8c187d26798a7ad..f1e347d06b414a815519fa5b3fc6d1a5b52ee875 100644 (file)
--- a/src/arch/null/utility.hh
+++ b/src/arch/null/utility.hh
@@ -52,8 +52,6 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
     return 0;
 }
 
-inline void initCPU(ThreadContext *tc, int cpuId) {}
-
 }
 
 #endif // __ARCH_NULL_UTILITY_HH__

diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index 6738c1289692f2e9542388585f288ca5c8b1315c..31869211a0e5868bb79dc576c138f6fc5d2f9b4c 100644 (file)
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -72,11 +72,4 @@ skipFunction(ThreadContext *tc)
     panic("Not Implemented for POWER");
 }
 
-void
-initCPU(ThreadContext *tc, int cpuId)
-{
-    panic("initCPU not implemented for POWER.\n");
-}
-
-
 } // namespace PowerISA

diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 3ae1d82f7c787f7882c5c9ae2b68889035928e3c..ce0f4ea76fa60727a142adfe998ba181a9d9eea4 100644 (file)
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -78,8 +78,6 @@ getExecutingAsid(ThreadContext *tc)
     return 0;
 }
 
-void initCPU(ThreadContext *, int cpuId);
-
 } // namespace PowerISA
 
 

diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 2ddba722bc8d22e32c4dc3e23894b9eeb4060e6b..25adb53a3522937fb1bdbfd581a6abd677f9da12 100644 (file)
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -57,7 +57,6 @@ if env['TARGET_ISA'] == 'riscv':
     Source('stacktrace.cc')
     Source('tlb.cc')
     Source('system.cc')
-    Source('utility.cc')
 
     Source('linux/process.cc')
     Source('linux/linux.cc')

diff --git a/src/arch/riscv/bare_metal/system.cc b/src/arch/riscv/bare_metal/system.cc
index 44e14e5ce83e673078237d02ae489dbedc7d14c7..8d4ea414d6a20ab6354c402a410312c63f2fa045 100644 (file)
--- a/src/arch/riscv/bare_metal/system.cc
+++ b/src/arch/riscv/bare_metal/system.cc
@@ -30,6 +30,7 @@
 
 #include "arch/riscv/bare_metal/system.hh"
 
+#include "arch/riscv/faults.hh"
 #include "base/loader/object_file.hh"
 
 BareMetalRiscvSystem::BareMetalRiscvSystem(Params *p)
@@ -54,6 +55,11 @@ BareMetalRiscvSystem::initState()
     // Call the initialisation of the super class
     RiscvSystem::initState();
 
+    for (auto *tc: threadContexts) {
+        RiscvISA::Reset().invoke(tc);
+        tc->activate();
+    }
+
     // load program sections into memory
     if (!bootloader->buildImage().write(physProxy)) {
         warn("could not load sections to memory");

diff --git a/src/arch/riscv/utility.cc b/src/arch/riscv/utility.cc
deleted file mode 100644 (file)
index 949d7c6..0000000
--- a/src/arch/riscv/utility.cc
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018 TU Dresden
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Robert Scheffel
- */
-
-#include "arch/riscv/utility.hh"
-
-#include "arch/riscv/faults.hh"
-
-namespace RiscvISA
-{
-
-void initCPU(ThreadContext *tc, int cpuId)
-{
-    Reset().invoke(tc);
-    tc->activate();
-}
-
-}

diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index f6e1f348ab6b683b5a63f6b6ccb4d7d284d1d346..1b8e2d93bf5a77234d76173bbab6c536fe313823 100644 (file)
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -181,11 +181,6 @@ getExecutingAsid(ThreadContext *tc)
     return 0;
 }
 
-/**
- * init Cpu function
- */
-void initCPU(ThreadContext *tc, int cpuId);
-
 } // namespace RiscvISA
 
 #endif // __ARCH_RISCV_UTILITY_HH__

diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc
index 1a809beba04881d2637a05ff6954d25b0080bb0b..1a495cceaab4f04e868fd98fe771b77fe77a9b42 100644 (file)
--- a/src/arch/sparc/system.cc
+++ b/src/arch/sparc/system.cc
@@ -30,6 +30,7 @@
 
 #include "arch/sparc/system.hh"
 
+#include "arch/sparc/faults.hh"
 #include "arch/vtophys.hh"
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
@@ -154,6 +155,14 @@ SparcSystem::initState()
 
     // @todo any fixup code over writing data in binaries on setting break
     // events on functions should happen here.
+
+    if (threadContexts.empty())
+        return;
+
+    // Other CPUs will get activated by IPIs.
+    auto *tc = threadContexts[0];
+    SparcISA::PowerOnReset().invoke(tc);
+    tc->activate();
 }
 
 SparcSystem::~SparcSystem()

diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 245f455e4424e96b68c3c0ebc4e2552418c5234c..e1ae563398c57f0c64bb89c5e983a85983dbda85 100644 (file)
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -253,16 +253,4 @@ skipFunction(ThreadContext *tc)
     tc->pcState(newPC);
 }
 
-
-void
-initCPU(ThreadContext *tc, int cpuId)
-{
-    // Other CPUs will get activated by IPIs.
-    if (cpuId != 0)
-        return;
-
-    PowerOnReset().invoke(tc);
-    tc->activate();
-}
-
 } // namespace SPARC_ISA

diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 74e0c11b86179c24bb36bc8b8d6b392c005c710e..6318b43567ec31955abe0f904c26108129039797 100644 (file)
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -62,8 +62,6 @@ inUserMode(ThreadContext *tc)
     return !(pstate.priv || hpstate.hpriv);
 }
 
-void initCPU(ThreadContext *tc, int cpuId);
-
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 
 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);

diff --git a/src/arch/x86/system.cc b/src/arch/x86/system.cc
index 096f10f5e2153273ca122aa6e679e91198f2cb5d..b0dab7bedd1d6e8fcd163287afd1e81fd4fd19b5 100644 (file)
--- a/src/arch/x86/system.cc
+++ b/src/arch/x86/system.cc
@@ -43,6 +43,7 @@
 
 #include "arch/x86/bios/intelmp.hh"
 #include "arch/x86/bios/smbios.hh"
+#include "arch/x86/faults.hh"
 #include "arch/x86/isa_traits.hh"
 #include "base/loader/object_file.hh"
 #include "cpu/thread_context.hh"
@@ -107,6 +108,19 @@ X86System::initState()
 {
     System::initState();
 
+    for (auto *tc: threadContexts) {
+        X86ISA::InitInterrupt(0).invoke(tc);
+
+        if (tc->contextId() == 0) {
+            tc->activate();
+        } else {
+            // This is an application processor (AP). It should be initialized
+            // to look like only the BIOS POST has run on it and put then put
+            // it into a halted state.
+            tc->suspend();
+        }
+    }
+
     if (!kernel)
         fatal("No kernel to load.\n");
 

diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 21765ceae32fb2ce5abec43aa8c1b0199f1d3011..6f91a176ecc2192f7e646c46e3e8fc754d9ff971 100644 (file)
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -71,21 +71,6 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
     }
 }
 
-void
-initCPU(ThreadContext *tc, int cpuId)
-{
-    InitInterrupt(0).invoke(tc);
-
-    if (cpuId == 0) {
-        tc->activate();
-    } else {
-        // This is an application processor (AP). It should be initialized to
-        // look like only the BIOS POST has run on it and put then put it into
-        // a halted state.
-        tc->suspend();
-    }
-}
-
 void
 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {

diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 88c7a17e41c8dee246bdc040d9f17ab421ca1966..7559b4bcaa662cbd93f47e6f9b4d6a3862f892f6 100644 (file)
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -69,8 +69,6 @@ namespace X86ISA
         }
     }
 
-    void initCPU(ThreadContext *tc, int cpuId);
-
     void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);

diff --git a/src/sim/system.cc b/src/sim/system.cc
index 368eb5419d3af8abebc8105d72e848db29f79fa8..b5b59ef6de52a970dfa18b8d1c3b7749ceaec738 100644 (file)
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -349,8 +349,6 @@ void
 System::initState()
 {
     if (FullSystem) {
-        for (auto *tc: threadContexts)
-            TheISA::initCPU(tc, tc->contextId());
         // Moved from the constructor to here since it relies on the
         // address map being resolved in the interconnect
         /**