projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
f993d18
)
optimization, all items should have same attributes
author
Miodrag Milanovic
<mmicko@gmail.com>
Thu, 25 Jun 2020 07:18:53 +0000
(09:18 +0200)
committer
Miodrag Milanovic
<mmicko@gmail.com>
Thu, 25 Jun 2020 07:18:53 +0000
(09:18 +0200)
frontends/verific/verific.cc
patch
|
blob
|
history
diff --git
a/frontends/verific/verific.cc
b/frontends/verific/verific.cc
index 89d734c40453b932fc51673a0fcaedd7a005e6d3..6637c214de35949fd9fee4a81201073ad6ecb9f2 100644
(file)
--- a/
frontends/verific/verific.cc
+++ b/
frontends/verific/verific.cc
@@
-1112,6
+1112,7
@@
void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
MapIter mibus;
FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
import_attributes(wire->attributes, net, nl);
+ break;
}
RTLIL::Const initval = Const(State::Sx, GetSize(wire));