Mem: Tidy up bus member variables types

This patch merely tidies up the types used for the bus member
variables. It also makes the constant ones const.

diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index d24cefa6290d327b6afab439275e3da314c41d1d..447fc723e5ab16136cc692fa39b06143a2204f51 100644 (file)
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -50,9 +50,9 @@ class BaseBus(MemObject):
     # Override the default clock
     clock = '1GHz'
     header_cycles = Param.Cycles(1, "cycles of overhead per transaction")
-    width = Param.Int(8, "bus width (bytes)")
-    block_size = Param.Int(64, "The default block size if not set by " \
-                               "any connected module")
+    width = Param.Unsigned(8, "bus width (bytes)")
+    block_size = Param.Unsigned(64, "The default block size if not set by " \
+                                    "any connected module")
 
     # The default port can be left unconnected, or be used to connect
     # a default slave port

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index ba45bfcb5ca5ca293c63049ac329bb1247a411e8..4dfcbad1ce9f7e7fdfa0b52feb9f6fed3d96f364 100644 (file)
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -61,15 +61,7 @@ BaseBus::BaseBus(const BaseBusParams *p)
       useDefaultRange(p->use_default_range),
       defaultBlockSize(p->block_size),
       cachedBlockSize(0), cachedBlockSizeValid(false)
-{
-    //width, clock period, and header cycles must be positive
-    if (width <= 0)
-        fatal("Bus width must be positive\n");
-    if (clock <= 0)
-        fatal("Bus clock period must be positive\n");
-    if (headerCycles <= 0)
-        fatal("Number of header cycles must be positive\n");
-}
+{}
 
 BaseBus::~BaseBus()
 {

diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 541e2f3635185d3ac5d56c9b7ef1031ee4d3eefa..95699cf22eae1adc8b289423ff68978ca8322ff8 100644 (file)
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -228,9 +228,9 @@ class BaseBus : public MemObject
     };
 
     /** cycles of overhead per transaction */
-    int headerCycles;
+    const Cycles headerCycles;
     /** the width of the bus in bytes */
-    int width;
+    const uint32_t width;
 
     typedef AddrRangeMap<PortID>::iterator PortMapIter;
     typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter;
@@ -346,10 +346,10 @@ class BaseBus : public MemObject
        address not handled by another port and not in default device's
        range will cause a fatal error.  If false, just send all
        addresses not handled by another port to default device. */
-    bool useDefaultRange;
+    const bool useDefaultRange;
 
-    unsigned defaultBlockSize;
-    unsigned cachedBlockSize;
+    const uint32_t defaultBlockSize;
+    uint32_t cachedBlockSize;
     bool cachedBlockSizeValid;
 
     BaseBus(const BaseBusParams *p);