---------- Begin Simulation Statistics ----------
sim_seconds 0.000727 # Number of seconds simulated
-sim_ticks 727072000 # Number of ticks simulated
-final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 727072500 # Number of ticks simulated
+final_tick 727072500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1546280 # Simulator instruction rate (inst/s)
-host_op_rate 1546201 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2248282899 # Simulator tick rate (ticks/s)
-host_mem_usage 227720 # Number of bytes of host memory used
-host_seconds 0.32 # Real time elapsed on the host
+host_inst_rate 639322 # Simulator instruction rate (inst/s)
+host_op_rate 639300 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 929601467 # Simulator tick rate (ticks/s)
+host_mem_usage 223596 # Number of bytes of host memory used
+host_seconds 0.78 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 35473791 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 39963030 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 75436821 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 35473791 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 35473791 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 35473791 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 39963030 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 75436821 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 718 # Transaction distribution
-system.membus.trans_dist::ReadResp 718 # Transaction distribution
-system.membus.trans_dist::ReadExReq 139 # Transaction distribution
-system.membus.trans_dist::ReadExResp 139 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 857 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 857 # Request fanout histogram
-system.membus.reqLayer0.occupancy 857000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 7713000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
+system.physmem.bw_read::cpu.inst 35473766 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 39963002 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 75436769 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 35473766 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 35473766 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 35473766 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 39963002 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 75436769 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 1454144 # number of cpu cycles simulated
+system.cpu.numCycles 1454145 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1454144 # Number of busy cycles
+system.cpu.num_busy_cycles 1454145 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 59023 # Number of branches fetched
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 500019 # Class of executed instruction
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 287.258890 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 287.258890 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
+system.cpu.dcache.overall_hits::total 180321 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
+system.cpu.dcache.overall_misses::total 454 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
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+system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16852500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 16852500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7436500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24289000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 24289000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24289000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 24289000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
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+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 265.012564 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 265.012564 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id
system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.icache.overall_misses::total 403 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 22165000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 22165000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 22165000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 22165000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 22165000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 22165000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 22165500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 22165500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55001.240695 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55001.240695 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55001.240695 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55001.240695 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55001.240695 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55001.240695 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21359000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 21359000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21359000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 21359000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21359000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 21359000 # number of overall MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 21561000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53501.240695 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53501.240695 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 481.542013 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 481.541188 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019216 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 216.521972 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses
system.cpu.l2cache.overall_misses::total 857 # number of overall misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16380000 # number of ReadReq miss cycles
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12600000 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::total 34280000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18160000 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 287.259400 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
-system.cpu.dcache.overall_hits::total 180321 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
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-system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 454 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 718 # Transaction distribution
+system.membus.trans_dist::ReadResp 718 # Transaction distribution
+system.membus.trans_dist::ReadExReq 139 # Transaction distribution
+system.membus.trans_dist::ReadExResp 139 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 857 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 857 # Request fanout histogram
+system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4285500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2852799 # Simulator instruction rate (inst/s)
-host_op_rate 2852705 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 356601416 # Simulator tick rate (ticks/s)
-host_mem_usage 239540 # Number of bytes of host memory used
-host_seconds 0.70 # Real time elapsed on the host
+host_inst_rate 1548972 # Simulator instruction rate (inst/s)
+host_op_rate 1548948 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 193626740 # Simulator tick rate (ticks/s)
+host_mem_usage 235568 # Number of bytes of host memory used
+host_seconds 1.29 # Real time elapsed on the host
sim_insts 2000004 # Number of instructions simulated
sim_ops 2000004 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 2872 # Transaction distribution
-system.membus.trans_dist::ReadResp 2872 # Transaction distribution
-system.membus.trans_dist::ReadExReq 556 # Transaction distribution
-system.membus.trans_dist::ReadExResp 556 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3428 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3428 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3428 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
-system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 1088 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1836 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 34048 # Number of tag accesses
-system.l2c.tags.data_accesses 34048 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
-system.l2c.Writeback_hits::total 116 # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu0.data 9 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu1.data 9 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu2.data 9 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu3.data 9 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
-system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu0.data 454 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu1.data 454 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu2.data 454 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu3.data 454 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
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-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes)
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-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 500019 # Class of executed instruction
-system.cpu0.icache.tags.replacements 152 # number of replacements
-system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
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-system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
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-system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits
-system.cpu0.icache.overall_hits::total 499556 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
-system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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+system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 2872 # Transaction distribution
+system.membus.trans_dist::ReadResp 2872 # Transaction distribution
+system.membus.trans_dist::ReadExReq 556 # Transaction distribution
+system.membus.trans_dist::ReadExResp 556 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3428 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3428 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 3428 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 0 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000729 # Number of seconds simulated
-sim_ticks 729024000 # Number of ticks simulated
-final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000728 # Number of seconds simulated
+sim_ticks 727903500 # Number of ticks simulated
+final_tick 727903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1431965 # Simulator instruction rate (inst/s)
-host_op_rate 1431947 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 521966515 # Simulator tick rate (ticks/s)
-host_mem_usage 239544 # Number of bytes of host memory used
-host_seconds 1.40 # Real time elapsed on the host
-sim_insts 1999959 # Number of instructions simulated
-sim_ops 1999959 # Number of ops (including micro ops) simulated
+host_inst_rate 639540 # Simulator instruction rate (inst/s)
+host_op_rate 639535 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 232760737 # Simulator tick rate (ticks/s)
+host_mem_usage 235576 # Number of bytes of host memory used
+host_seconds 3.13 # Real time elapsed on the host
+sim_insts 1999978 # Number of instructions simulated
+sim_ops 1999978 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 35378808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39856027 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35378808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 39856027 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 35378808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 39856027 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 35378808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 39856027 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 300939338 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 141515231 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39856027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 39856027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 39856027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 39856027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 300939338 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 2872 # Transaction distribution
-system.membus.trans_dist::ReadResp 2872 # Transaction distribution
-system.membus.trans_dist::ReadExReq 556 # Transaction distribution
-system.membus.trans_dist::ReadExResp 556 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3431 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3431 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3431 # Request fanout histogram
-system.membus.reqLayer0.occupancy 4229968 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 31051500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 4.3 # Layer utilization (%)
+system.physmem.bw_read::cpu0.inst 35433268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 39917379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35433268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 39917379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 35433268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 39917379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 35433268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 39917379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 301402590 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 35433268 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35433268 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 35433268 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 35433268 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 141733073 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 35433268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 39917379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 35433268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 39917379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 35433268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 39917379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 35433268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 39917379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 301402590 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use
-system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2904 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 34048 # Number of tag accesses
-system.l2c.tags.data_accesses 34048 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
-system.l2c.Writeback_hits::total 116 # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu0.data 9 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu1.data 9 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu2.data 9 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu3.data 9 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
-system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
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-system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794 # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40093.650794 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302 # average ReadReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40176.258993 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993 # average ReadExReq mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
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-system.toL2Bus.snoops 0 # Total snoops (count)
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-system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
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-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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-system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram
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system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 500001 # Number of instructions committed
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system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.Branches 59023 # Number of branches fetched
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 500019 # Class of executed instruction
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system.cpu0.dcache.tags.replacements 61 # number of replacements
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system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
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system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
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system.cpu0.dcache.overall_misses::total 463 # number of overall misses
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
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system.cpu1.dtb.data_misses 18 # DTB misses
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system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
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-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency
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-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49573.434125 # average overall miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average overall mshr miss latency
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system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 124433 # DTB read hits
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system.cpu2.dtb.read_misses 8 # DTB read misses
system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_accesses 124441 # DTB read accesses
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system.cpu2.dtb.write_hits 56339 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
system.cpu2.dtb.write_acv 0 # DTB write access violations
system.cpu2.dtb.write_accesses 56349 # DTB write accesses
-system.cpu2.dtb.data_hits 180772 # DTB hits
+system.cpu2.dtb.data_hits 180774 # DTB hits
system.cpu2.dtb.data_misses 18 # DTB misses
system.cpu2.dtb.data_acv 0 # DTB access violations
-system.cpu2.dtb.data_accesses 180790 # DTB accesses
-system.cpu2.itb.fetch_hits 500005 # ITB hits
+system.cpu2.dtb.data_accesses 180792 # DTB accesses
+system.cpu2.itb.fetch_hits 500011 # ITB hits
system.cpu2.itb.fetch_misses 13 # ITB misses
system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_accesses 500018 # ITB accesses
+system.cpu2.itb.fetch_accesses 500024 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.workload.num_syscalls 18 # Number of system calls
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+system.cpu2.numCycles 1455807 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 499986 # Number of instructions committed
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-system.cpu2.num_int_alu_accesses 474674 # Number of integer alu accesses
+system.cpu2.committedInsts 499992 # Number of instructions committed
+system.cpu2.committedOps 499992 # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses 474680 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu2.num_func_calls 14357 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 474674 # number of integer instructions
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system.cpu2.num_fp_insts 32 # number of float instructions
-system.cpu2.num_int_register_reads 654263 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 371529 # number of times the integer registers were written
+system.cpu2.num_int_register_reads 654271 # number of times the integer registers were read
+system.cpu2.num_int_register_writes 371535 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
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-system.cpu2.num_load_insts 124441 # Number of load instructions
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system.cpu2.num_store_insts 56349 # Number of store instructions
system.cpu2.num_idle_cycles 0 # Number of idle cycles
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system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0 # Percentage of idle cycles
system.cpu2.Branches 59022 # Number of branches fetched
system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
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system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::MemRead 124441 24.89% 88.73% # Class of executed instruction
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system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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+system.cpu2.icache.overall_misses::total 463 # number of overall misses
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+system.cpu2.icache.overall_miss_latency::total 22957500 # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst 500011 # number of ReadReq accesses(hits+misses)
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+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49584.233261 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 49584.233261 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49584.233261 # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 49584.233261 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49584.233261 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 49584.233261 # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu2.icache.fast_writes 0 # number of fast writes performed
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+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
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+system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22263000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total 22263000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22263000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total 22263000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22263000 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 22263000 # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
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+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
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+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48084.233261 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 48084.233261 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 48084.233261 # average overall mshr miss latency
+system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.dtb.fetch_hits 0 # ITB hits
+system.cpu3.dtb.fetch_misses 0 # ITB misses
+system.cpu3.dtb.fetch_acv 0 # ITB acv
+system.cpu3.dtb.fetch_accesses 0 # ITB accesses
+system.cpu3.dtb.read_hits 124433 # DTB read hits
+system.cpu3.dtb.read_misses 8 # DTB read misses
+system.cpu3.dtb.read_acv 0 # DTB read access violations
+system.cpu3.dtb.read_accesses 124441 # DTB read accesses
+system.cpu3.dtb.write_hits 56339 # DTB write hits
+system.cpu3.dtb.write_misses 10 # DTB write misses
+system.cpu3.dtb.write_acv 0 # DTB write access violations
+system.cpu3.dtb.write_accesses 56349 # DTB write accesses
+system.cpu3.dtb.data_hits 180772 # DTB hits
+system.cpu3.dtb.data_misses 18 # DTB misses
+system.cpu3.dtb.data_acv 0 # DTB access violations
+system.cpu3.dtb.data_accesses 180790 # DTB accesses
+system.cpu3.itb.fetch_hits 500007 # ITB hits
+system.cpu3.itb.fetch_misses 13 # ITB misses
+system.cpu3.itb.fetch_acv 0 # ITB acv
+system.cpu3.itb.fetch_accesses 500020 # ITB accesses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.read_acv 0 # DTB read access violations
system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.workload.num_syscalls 18 # Number of system calls
-system.cpu3.numCycles 1458048 # number of cpu cycles simulated
+system.cpu3.numCycles 1455807 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 499979 # Number of instructions committed
-system.cpu3.committedOps 499979 # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses 474668 # Number of integer alu accesses
+system.cpu3.committedInsts 499988 # Number of instructions committed
+system.cpu3.committedOps 499988 # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses 474676 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu3.num_func_calls 14357 # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 474668 # number of integer instructions
+system.cpu3.num_conditional_control_insts 38179 # number of instructions that are conditional controls
+system.cpu3.num_int_insts 474676 # number of integer instructions
system.cpu3.num_fp_insts 32 # number of float instructions
-system.cpu3.num_int_register_reads 654256 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 371524 # number of times the integer registers were written
+system.cpu3.num_int_register_reads 654266 # number of times the integer registers were read
+system.cpu3.num_int_register_writes 371531 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu3.num_mem_refs 180788 # number of memory refs
-system.cpu3.num_load_insts 124439 # Number of load instructions
+system.cpu3.num_mem_refs 180790 # number of memory refs
+system.cpu3.num_load_insts 124441 # Number of load instructions
system.cpu3.num_store_insts 56349 # Number of store instructions
system.cpu3.num_idle_cycles 0 # Number of idle cycles
-system.cpu3.num_busy_cycles 1458048 # Number of busy cycles
+system.cpu3.num_busy_cycles 1455807 # Number of busy cycles
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.Branches 59020 # Number of branches fetched
+system.cpu3.Branches 59022 # Number of branches fetched
system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu3.op_class::IntAlu 300371 60.07% 63.84% # Class of executed instruction
+system.cpu3.op_class::IntAlu 300378 60.07% 63.84% # Class of executed instruction
system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::MemRead 124439 24.89% 88.73% # Class of executed instruction
+system.cpu3.op_class::MemRead 124441 24.89% 88.73% # Class of executed instruction
system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::total 499997 # Class of executed instruction
-system.cpu3.icache.tags.replacements 152 # number of replacements
-system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor
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-system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy
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-system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 500461 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 500461 # Number of data accesses
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-system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
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-system.cpu3.icache.overall_misses::total 463 # number of overall misses
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-system.cpu3.icache.ReadReq_miss_latency::total 23123000 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst 23123000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total 23123000 # number of demand (read+write) miss cycles
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-system.cpu3.icache.overall_miss_latency::total 23123000 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 499998 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 499998 # number of ReadReq accesses(hits+misses)
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-system.cpu3.icache.overall_accesses::total 499998 # number of overall (read+write) accesses
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-system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
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-system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49941.684665 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 49941.684665 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 49941.684665 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 49941.684665 # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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-system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
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-system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
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-system.cpu3.icache.demand_mshr_miss_latency::total 22197000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22197000 # number of overall MSHR miss cycles
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-system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
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-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 47941.684665 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.op_class::total 500006 # Class of executed instruction
system.cpu3.dcache.tags.replacements 61 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse 273.589931 # Cycle average of tags in use
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system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks.
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system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
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-system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits
+system.cpu3.dcache.tags.tag_accesses 723551 # Number of tag accesses
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system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
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-system.cpu3.dcache.overall_hits::total 180307 # number of overall hits
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+system.cpu3.dcache.overall_hits::total 180309 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
system.cpu3.dcache.overall_misses::total 463 # number of overall misses
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-system.cpu3.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7669500 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40528.535980 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40503.174603 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40534.739454 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40503.174603 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40512.012535 # average ReadReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40500 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40500 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40517.369727 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40528.535980 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40502.202643 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40534.739454 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40502.202643 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40510.064177 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40517.369727 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40528.535980 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40502.202643 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40534.739454 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40502.202643 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40510.064177 # average overall mshr miss latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 2872 # Transaction distribution
+system.membus.trans_dist::ReadResp 2872 # Transaction distribution
+system.membus.trans_dist::ReadExReq 556 # Transaction distribution
+system.membus.trans_dist::ReadExResp 556 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3437 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3437 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 3437 # Request fanout histogram
+system.membus.reqLayer0.occupancy 3440968 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 17142500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 2.4 # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 0 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2026000 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff