MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASK

Complement commit e407c74b5b60 ("Support for MIPS R5900 (Sony Playstation
2)"), <https://sourceware.org/ml/binutils/2012-12/msg00240.html>, and
commit 2c62985659da ("MIPS: Add Octeon 3 support") and update the chip
mask accordingly.

	include/
	* opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.

diff --git a/include/ChangeLog b/include/ChangeLog
index 7d37b15c239fb7308478660837b015aea364b559..00cebb6b9d772ed97d5b96fe1d029e4506e5c31e 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
+
 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 
        * opcode/mips.h (ASE_DSPR3): Add a comment.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 08bc24f56d0912bb9862fa8f8a3a6ca297947b53..160fc9166f59dc4cb05595fecde750d78cd9ef8c 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1194,7 +1194,7 @@ static const unsigned int mips_isa_table[] = {
 #undef ISAF
 
 /* Masks used for Chip specific instructions.  */
-#define INSN_CHIP_MASK           0xc3ff0f20
+#define INSN_CHIP_MASK           0xc3ff4f60
 
 /* Cavium Networks Octeon instructions.  */
 #define INSN_OCTEON              0x00000800