ttn: Use 1-bit NIR comparison opcodes

We shouldn't be using the versions that output a 32-bit boolean, since
nir_opt_algebraic won't optimize them as well. Drivers will lower these
to the 32-bit versions after optimizing, if appropriate. Also, this will
make implementing 64-bit comparisons easier.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 9c2639c221f44694f3dbf9fd20b671dfe81af92b..19b5755cad22b756936cc9c4feff3396124beba7 100644 (file)
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -838,20 +838,6 @@ ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
    return def;
 }
 
-static void
-ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
-{
-   unsigned num_srcs = nir_op_infos[op].num_inputs;
-   nir_alu_instr *instr = nir_alu_instr_create(b->shader, op);
-   unsigned i;
-
-   for (i = 0; i < num_srcs; i++)
-      instr->src[i].src = nir_src_for_ssa(src[i]);
-
-   instr->dest = dest;
-   nir_builder_instr_insert(b, &instr->instr);
-}
-
 static void
 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
                      nir_ssa_def *def, unsigned write_mask)
@@ -874,6 +860,15 @@ ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
    ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
 }
 
+static void
+ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
+{
+   nir_ssa_def *def = nir_build_alu_src_arr(b, op, src);
+   if (def->bit_size == 1)
+      def = nir_ineg(b, nir_b2i(b, def, 32));
+   ttn_move_dest(b, dest, def);
+}
+
 static void
 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
 {
@@ -1636,10 +1631,10 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
    [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
 
    [TGSI_OPCODE_NOP] = 0,
-   [TGSI_OPCODE_FSEQ] = nir_op_feq32,
-   [TGSI_OPCODE_FSGE] = nir_op_fge32,
-   [TGSI_OPCODE_FSLT] = nir_op_flt32,
-   [TGSI_OPCODE_FSNE] = nir_op_fne32,
+   [TGSI_OPCODE_FSEQ] = nir_op_feq,
+   [TGSI_OPCODE_FSGE] = nir_op_fge,
+   [TGSI_OPCODE_FSLT] = nir_op_flt,
+   [TGSI_OPCODE_FSNE] = nir_op_fne,
 
    [TGSI_OPCODE_KILL_IF] = 0,
 
@@ -1650,9 +1645,9 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
    [TGSI_OPCODE_IMAX] = nir_op_imax,
    [TGSI_OPCODE_IMIN] = nir_op_imin,
    [TGSI_OPCODE_INEG] = nir_op_ineg,
-   [TGSI_OPCODE_ISGE] = nir_op_ige32,
+   [TGSI_OPCODE_ISGE] = nir_op_ige,
    [TGSI_OPCODE_ISHR] = nir_op_ishr,
-   [TGSI_OPCODE_ISLT] = nir_op_ilt32,
+   [TGSI_OPCODE_ISLT] = nir_op_ilt,
    [TGSI_OPCODE_F2U] = nir_op_f2u32,
    [TGSI_OPCODE_U2F] = nir_op_u2f32,
    [TGSI_OPCODE_UADD] = nir_op_iadd,
@@ -1662,11 +1657,11 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
    [TGSI_OPCODE_UMIN] = nir_op_umin,
    [TGSI_OPCODE_UMOD] = nir_op_umod,
    [TGSI_OPCODE_UMUL] = nir_op_imul,
-   [TGSI_OPCODE_USEQ] = nir_op_ieq32,
-   [TGSI_OPCODE_USGE] = nir_op_uge32,
+   [TGSI_OPCODE_USEQ] = nir_op_ieq,
+   [TGSI_OPCODE_USGE] = nir_op_uge,
    [TGSI_OPCODE_USHR] = nir_op_ushr,
-   [TGSI_OPCODE_USLT] = nir_op_ult32,
-   [TGSI_OPCODE_USNE] = nir_op_ine32,
+   [TGSI_OPCODE_USLT] = nir_op_ult,
+   [TGSI_OPCODE_USNE] = nir_op_ine,
 
    [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
    [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */