genrtlil: fix signed port connection codegen failures

This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index b8bfdf65e8471a391f0877e3a43670f38d16dff0..24f5e1bef90566ae940fdc13bc8ce18e2dd373e4 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -49,6 +49,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width
 
        RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
        wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);
+       wire->is_signed = that->is_signed;
 
        if (gen_attributes)
                for (auto &attr : that->attributes) {
@@ -80,6 +81,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 
        RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
        wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);
+       wire->is_signed = that->is_signed;
 
        if (that != NULL)
                for (auto &attr : that->attributes) {
@@ -1050,6 +1052,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                        RTLIL::Const val = children[0]->bitsAsConst();
                        RTLIL::Wire *wire = current_module->addWire(str, GetSize(val));
                        current_module->connect(wire, val);
+                       wire->is_signed = children[0]->is_signed;
 
                        wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
                        wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1;
@@ -1551,6 +1554,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
                        int mem_width, mem_size, addr_bits;
                        is_signed = id2ast->is_signed;
+                       wire->is_signed = is_signed;
                        id2ast->meminfo(mem_width, mem_size, addr_bits);
 
                        RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
@@ -1740,7 +1744,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                                        // non-trivial signed nodes are indirected through
                                                        // signed wires to enable sign extension
                                                        RTLIL::IdString wire_name = NEW_ID;
-                                                       RTLIL::Wire *wire = current_module->addWire(wire_name, arg->bits.size());
+                                                       RTLIL::Wire *wire = current_module->addWire(wire_name, GetSize(sig));
                                                        wire->is_signed = true;
                                                        current_module->connect(wire, sig);
                                                        sig = wire;

diff --git a/tests/various/port_sign_extend.v b/tests/various/port_sign_extend.v
index 4462682687298a4df0e3aaa72725a82477cc063a..813ceb503124708396f5941d88fb579226311638 100644 (file)
--- a/tests/various/port_sign_extend.v
+++ b/tests/various/port_sign_extend.v
@@ -24,8 +24,8 @@ module PassThrough(a, b);
        assign b = a;
 endmodule
 
-module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2);
-       output wire [3:0] o1, o2, o3, o4, o5, o6;
+module act(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2);
+       output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9;
 
        // unsigned constant
        PassThrough pt1(1'b1, o1);
@@ -52,6 +52,17 @@ module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2);
        wire signed [2:0] tmp6b = 3'b001;
        PassThrough pt6(tmp6a ? tmp6a : tmp6b, o6);
 
+       wire signed [2:0] tmp7 = 3'b011;
+       PassThrough pt7(~tmp7, o7);
+
+       reg signed [2:0] tmp8 [0:0];
+       initial tmp8[0] = 3'b101;
+       PassThrough pt8(tmp8[0], o8);
+
+       wire signed [2:0] tmp9a = 3'b100;
+       wire signed [1:0] tmp9b = 2'b11;
+       PassThrough pt9(0 ? tmp9a : tmp9b, o9);
+
        output wire [2:0] yay1, nay1;
        GeneratorSigned1   os1(yay1);
        GeneratorUnsigned1 ou1(nay1);
@@ -61,8 +72,8 @@ module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2);
        GeneratorUnsigned2 ou2(nay2);
 endmodule
 
-module ref(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2);
-       output wire [3:0] o1, o2, o3, o4, o5, o6;
+module ref(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2);
+       output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9;
 
        assign o1 = 4'b0001;
        assign o2 = 4'b0001;
@@ -70,6 +81,9 @@ module ref(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2);
        assign o4 = 4'b1111;
        assign o5 = 4'b1110;
        assign o6 = 4'b1100;
+       assign o7 = 4'b1100;
+       assign o8 = 4'b1101;
+       assign o9 = 4'b1111;
 
        output wire [2:0] yay1, nay1;
        assign yay1 = 3'b111;

diff --git a/tests/various/port_sign_extend.ys b/tests/various/port_sign_extend.ys
index 0a6a9381038ae118252aa399d413801ff4a1e12c..6d1adf7f3506f68c6f03ce867d5e2b574c62d526 100644 (file)
--- a/tests/various/port_sign_extend.ys
+++ b/tests/various/port_sign_extend.ys
@@ -1,22 +1,29 @@
-read_verilog port_sign_extend.v
+read_verilog -nomem2reg port_sign_extend.v
 hierarchy
 flatten
+proc
+memory
 equiv_make ref act equiv
 equiv_simple
 equiv_status -assert
 
 delete
 
-read_verilog port_sign_extend.v
+read_verilog -nomem2reg port_sign_extend.v
 flatten
+proc
+memory
 equiv_make ref act equiv
 equiv_simple
 equiv_status -assert
 
 delete
 
-read_verilog port_sign_extend.v
+read_verilog -nomem2reg port_sign_extend.v
 hierarchy
+proc
+memory
 equiv_make ref act equiv
 prep -flatten -top equiv
+equiv_induct
 equiv_status -assert