hdl.dsl: allow adding submodules with computed name, like with domains.

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index 03e7e231994b583e0f4b06d11d97315f30b7e5f1..30629c4ae183842deac6e6219eb314a8537053a2 100644 (file)
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -83,6 +83,9 @@ class _ModuleBuilderSubmodules:
     def __setattr__(self, name, submodule):
         self._builder._add_submodule(submodule, name)
 
+    def __setitem__(self, name, value):
+        return self.__setattr__(name, value)
+
 
 class _ModuleBuilderDomainSet:
     def __init__(self, builder):

diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index 26775827a6494fa107c75a62e4cfc0d172b38e94..0e703e0c995b94db5fdef07830cae834318072ec 100644 (file)
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -505,6 +505,12 @@ class DSLTestCase(FHDLTestCase):
         m1.submodules.foo = m2
         self.assertEqual(m1._submodules, [(m2, "foo")])
 
+    def test_submodule_named_index(self):
+        m1 = Module()
+        m2 = Module()
+        m1.submodules["foo"] = m2
+        self.assertEqual(m1._submodules, [(m2, "foo")])
+
     def test_submodule_wrong(self):
         m = Module()
         with self.assertRaises(TypeError,