if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
continue;
RTLIL::SigSpec &signal = (*it4)->signal;
- for (size_t i = 0; i < signal.__chunks.size(); i++) {
- if (signal.__chunks[i].wire == wire)
+ for (size_t i = 0; i < signal.chunks().size(); i++) {
+ if (signal.chunks()[i].wire == wire)
is_clksignal = true;
}
}
const char *cstr(RTLIL::SigSpec sig)
{
sig.optimize();
- log_assert(sig.__width == 1);
+ log_assert(sig.size() == 1);
- if (sig.__chunks.at(0).wire == NULL)
- return sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S1 ? "$true" : "$false";
+ if (sig.chunks().at(0).wire == NULL)
+ return sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1 ? "$true" : "$false";
- std::string str = RTLIL::unescape_id(sig.__chunks.at(0).wire->name);
+ std::string str = RTLIL::unescape_id(sig.chunks().at(0).wire->name);
for (size_t i = 0; i < str.size(); i++)
if (str[i] == '#' || str[i] == '=')
str[i] = '?';
- if (sig.__chunks.at(0).wire->width != 1)
- str += stringf("[%d]", sig.__chunks.at(0).offset);
+ if (sig.chunks().at(0).wire->width != 1)
+ str += stringf("[%d]", sig.chunks().at(0).offset);
cstr_buf.push_back(str);
return cstr_buf.back().c_str();
fprintf(f, ".names");
auto &inputs = cell->connections.at("\\I");
auto width = cell->parameters.at("\\WIDTH").as_int();
- log_assert(inputs.__width == width);
- for (int i = 0; i < inputs.__width; i++) {
+ log_assert(inputs.size() == width);
+ for (int i = 0; i < inputs.size(); i++) {
fprintf(f, " %s", cstr(inputs.extract(i, 1)));
}
auto &output = cell->connections.at("\\O");
- log_assert(output.__width == 1);
+ log_assert(output.size() == 1);
fprintf(f, " %s", cstr(output));
fprintf(f, "\n");
auto mask = cell->parameters.at("\\LUT").as_string();
fprintf(f, ".%s %s", subckt_or_gate(cell->type), cstr(cell->type));
for (auto &conn : cell->connections)
- for (int i = 0; i < conn.second.__width; i++) {
- if (conn.second.__width == 1)
+ for (int i = 0; i < conn.second.size(); i++) {
+ if (conn.second.size() == 1)
fprintf(f, " %s", cstr(conn.first));
else
fprintf(f, " %s[%d]", cstr(conn.first), i);
}
for (auto &conn : module->connections)
- for (int i = 0; i < conn.first.__width; i++)
+ for (int i = 0; i < conn.first.size(); i++)
if (config->conn_mode)
fprintf(f, ".conn %s %s\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1)));
else if (!config->buf_type.empty())
RTLIL::SigSpec* cell_output = get_cell_output(cell);
int cell_line = dump_cell(cell);
- if(dep_set.size()==1 && wire->width == cell_output->__width)
+ if(dep_set.size()==1 && wire->width == cell_output->size())
{
wire_line = cell_line;
break;
{
int prev_wire_line=0; //previously dumped wire line
int start_bit=0;
- for(unsigned j=0; j<cell_output->__chunks.size(); ++j)
+ for(unsigned j=0; j<cell_output->chunks().size(); ++j)
{
- start_bit+=cell_output->__chunks[j].width;
- if(cell_output->__chunks[j].wire->name == wire->name)
+ start_bit+=cell_output->chunks()[j].width;
+ if(cell_output->chunks()[j].wire->name == wire->name)
{
prev_wire_line = wire_line;
wire_line = ++line_num;
- str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->__chunks[j].width,
- cell_line, start_bit-1, start_bit-cell_output->__chunks[j].width);
+ str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks()[j].width,
+ cell_line, start_bit-1, start_bit-cell_output->chunks()[j].width);
fprintf(f, "%s\n", str.c_str());
- wire_width += cell_output->__chunks[j].width;
+ wire_width += cell_output->chunks()[j].width;
if(prev_wire_line!=0)
{
++line_num;
{
log(" - checking sigmap\n");
RTLIL::SigSpec s = RTLIL::SigSpec(wire);
- wire_line = dump_sigspec(&s, s.__width);
+ wire_line = dump_sigspec(&s, s.size());
line_ref[wire->name]=wire_line;
}
line_ref[wire->name]=wire_line;
auto it = sig_ref.find(s);
if(it == std::end(sig_ref))
{
- if (s.__chunks.size() == 1)
+ if (s.chunks().size() == 1)
{
- l = dump_sigchunk(&s.__chunks[0]);
+ l = dump_sigchunk(&s.chunks()[0]);
}
else
{
int l1, l2, w1, w2;
- l1 = dump_sigchunk(&s.__chunks[0]);
+ l1 = dump_sigchunk(&s.chunks()[0]);
log_assert(l1>0);
- w1 = s.__chunks[0].width;
- for (unsigned i=1; i < s.__chunks.size(); ++i)
+ w1 = s.chunks()[0].width;
+ for (unsigned i=1; i < s.chunks().size(); ++i)
{
- l2 = dump_sigchunk(&s.__chunks[i]);
+ l2 = dump_sigchunk(&s.chunks()[i]);
log_assert(l2>0);
- w2 = s.__chunks[i].width;
+ w2 = s.chunks()[i].width;
++line_num;
str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1);
fprintf(f, "%s\n", str.c_str());
l = it->second;
}
- if (expected_width != s.__width)
+ if (expected_width != s.size())
{
log(" - changing width of sigspec\n");
//TODO: this block may not be needed anymore, due to explicit type conversion by "splice" command
- if(expected_width > s.__width)
+ if(expected_width > s.size())
{
//TODO: case the signal is signed
++line_num;
- str = stringf ("%d zero %d", line_num, expected_width - s.__width);
+ str = stringf ("%d zero %d", line_num, expected_width - s.size());
fprintf(f, "%s\n", str.c_str());
++line_num;
str = stringf ("%d concat %d %d %d", line_num, expected_width, line_num-1, l);
fprintf(f, "%s\n", str.c_str());
l = line_num;
}
- else if(expected_width < s.__width)
+ else if(expected_width < s.size())
{
++line_num;
str = stringf ("%d slice %d %d %d %d;3", line_num, expected_width, l, expected_width-1, 0);
log("writing assert cell - %s\n", cstr(cell->type));
const RTLIL::SigSpec* expr = &cell->connections.at(RTLIL::IdString("\\A"));
const RTLIL::SigSpec* en = &cell->connections.at(RTLIL::IdString("\\EN"));
- log_assert(expr->__width == 1);
- log_assert(en->__width == 1);
+ log_assert(expr->size() == 1);
+ log_assert(en->size() == 1);
int expr_line = dump_sigspec(expr, 1);
int en_line = dump_sigspec(en, 1);
int one_line = ++line_num;
const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q"));
int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width);
unsigned start_bit = 0;
- for(unsigned i=0; i<cell_output->__chunks.size(); ++i)
+ for(unsigned i=0; i<cell_output->chunks().size(); ++i)
{
- output_width = cell_output->__chunks[i].width;
- log_assert( output_width == cell_output->__chunks[i].wire->width);//full reg is given the next value
- int reg = dump_wire(cell_output->__chunks[i].wire);//register
+ output_width = cell_output->chunks()[i].width;
+ log_assert( output_width == cell_output->chunks()[i].wire->width);//full reg is given the next value
+ int reg = dump_wire(cell_output->chunks()[i].wire);//register
int slice = value;
- if(cell_output->__chunks.size()>1)
+ if(cell_output->chunks().size()>1)
{
start_bit+=output_width;
slice = ++line_num;
log("writing slice cell\n");
const RTLIL::SigSpec* input = &cell->connections.at(RTLIL::IdString("\\A"));
int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
- log_assert(input->__width == input_width);
+ log_assert(input->size() == input_width);
int input_line = dump_sigspec(input, input_width);
const RTLIL::SigSpec* output = &cell->connections.at(RTLIL::IdString("\\Y"));
int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
- log_assert(output->__width == output_width);
+ log_assert(output->size() == output_width);
int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();
++line_num;
str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset);
log("writing concat cell\n");
const RTLIL::SigSpec* input_a = &cell->connections.at(RTLIL::IdString("\\A"));
int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
- log_assert(input_a->__width == input_a_width);
+ log_assert(input_a->size() == input_a_width);
int input_a_line = dump_sigspec(input_a, input_a_width);
const RTLIL::SigSpec* input_b = &cell->connections.at(RTLIL::IdString("\\B"));
int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
- log_assert(input_b->__width == input_b_width);
+ log_assert(input_b->size() == input_b_width);
int input_b_line = dump_sigspec(input_b, input_b_width);
++line_num;
str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width,
log(" - %s\n", cstr(it->second->type));
if (cell->type == "$memrd")
{
- for(unsigned i=0; i<output_sig->__chunks.size(); ++i)
+ for(unsigned i=0; i<output_sig->chunks().size(); ++i)
{
- RTLIL::Wire *w = output_sig->__chunks[i].wire;
+ RTLIL::Wire *w = output_sig->chunks()[i].wire;
RTLIL::IdString wire_id = w->name;
- inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i]));
+ inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
}
}
else if(cell->type == "$memwr")
}
else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
{
- RTLIL::IdString wire_id = output_sig->__chunks[0].wire->name;
- for(unsigned i=0; i<output_sig->__chunks.size(); ++i)
+ RTLIL::IdString wire_id = output_sig->chunks()[0].wire->name;
+ for(unsigned i=0; i<output_sig->chunks().size(); ++i)
{
- RTLIL::Wire *w = output_sig->__chunks[i].wire;
+ RTLIL::Wire *w = output_sig->chunks()[i].wire;
RTLIL::IdString wire_id = w->name;
- inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i]));
+ inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
basic_wires[wire_id] = true;
}
}
else
{
- for(unsigned i=0; i<output_sig->__chunks.size(); ++i)
+ for(unsigned i=0; i<output_sig->chunks().size(); ++i)
{
- RTLIL::Wire *w = output_sig->__chunks[i].wire;
+ RTLIL::Wire *w = output_sig->chunks()[i].wire;
RTLIL::IdString wire_id = w->name;
- inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i]));
+ inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
}
}
}
if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
lib_cell_ports[cell->type];
for (auto p : cell->connections) {
- if (p.second.__width > 1)
+ if (p.second.size() > 1)
log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n",
RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
lib_cell_ports[cell->type].insert(p.first);
for (auto &p : cell->connections) {
RTLIL::SigSpec sig = sigmap(p.second);
sig.expand();
- for (int i = 0; i < sig.__width; i++) {
- RTLIL::SigSpec sigbit(sig.__chunks.at(i));
- if (sig.__width == 1)
+ for (int i = 0; i < sig.size(); i++) {
+ RTLIL::SigSpec sigbit(sig.chunks().at(i));
+ if (sig.size() == 1)
net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
else
net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name)));
for (auto &it : net_join_db) {
RTLIL::SigSpec sig = it.first;
sig.optimize();
- log_assert(sig.__width == 1);
- if (sig.__chunks.at(0).wire == NULL) {
- if (sig.__chunks.at(0).data.bits.at(0) != RTLIL::State::S0 && sig.__chunks.at(0).data.bits.at(0) != RTLIL::State::S1)
+ log_assert(sig.size() == 1);
+ if (sig.chunks().at(0).wire == NULL) {
+ if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1)
continue;
}
std::string netname = log_signal(sig);
fprintf(f, " (net %s (joined\n", EDIF_DEF(netname));
for (auto &ref : it.second)
fprintf(f, " %s\n", ref.c_str());
- if (sig.__chunks.at(0).wire == NULL) {
- if (sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S0)
+ if (sig.chunks().at(0).wire == NULL) {
+ if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S0)
fprintf(f, " (portRef G (instanceRef GND))\n");
- if (sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S1)
+ if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1)
fprintf(f, " (portRef P (instanceRef VCC))\n");
}
fprintf(f, " ))\n");
void ILANG_BACKEND::dump_sigspec(FILE *f, const RTLIL::SigSpec &sig, bool autoint)
{
- if (sig.__chunks.size() == 1) {
- dump_sigchunk(f, sig.__chunks[0], autoint);
+ if (sig.chunks().size() == 1) {
+ dump_sigchunk(f, sig.chunks()[0], autoint);
} else {
fprintf(f, "{ ");
- for (auto it = sig.__chunks.rbegin(); it != sig.__chunks.rend(); it++) {
+ for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) {
dump_sigchunk(f, *it, false);
fprintf(f, " ");
}
if (only_selected) {
RTLIL::SigSpec sigs = it->first;
sigs.append(it->second);
- for (auto &c : sigs.__chunks) {
+ for (auto &c : sigs.chunks()) {
if (c.wire == NULL || !design->selected(module, c.wire))
continue;
show_conn = true;
{
sig.optimize();
- if (sig.__chunks.size() != 1)
+ if (sig.chunks().size() != 1)
error:
log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig));
- conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.__width, sig.__width, sig.__width));
+ conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
- if (sig.__chunks[0].wire == NULL) {
- celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.__width, sig.__width, sig.__width));
- constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.__width, sig.__chunks[0].data.as_int(),
- sig.__width, sig.__width, sig.__chunks[0].data.as_int(), sig.__chunks[0].data.as_int()));
- return stringf("CONST_%d_0x%x", sig.__width, sig.__chunks[0].data.as_int());
+ if (sig.chunks()[0].wire == NULL) {
+ celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.size(), sig.size(), sig.size()));
+ constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.size(), sig.chunks()[0].data.as_int(),
+ sig.size(), sig.size(), sig.chunks()[0].data.as_int(), sig.chunks()[0].data.as_int()));
+ return stringf("CONST_%d_0x%x", sig.size(), sig.chunks()[0].data.as_int());
}
- if (sig.__chunks[0].offset != 0 || sig.__width != sig.__chunks[0].wire->width)
+ if (sig.chunks()[0].offset != 0 || sig.size() != sig.chunks()[0].wire->width)
goto error;
- return RTLIL::unescape_id(sig.__chunks[0].wire->name);
+ return RTLIL::unescape_id(sig.chunks()[0].wire->name);
}
struct IntersynthBackend : public Backend {
node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
for (auto &port : cell->connections) {
RTLIL::SigSpec sig = sigmap(port.second);
- if (sig.__width != 0) {
- conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.__width, sig.__width, sig.__width));
- celltype_code += stringf(" b%d %s%s", sig.__width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
+ if (sig.size() != 0) {
+ conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
+ celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
}
}
static void print_spice_net(FILE *f, RTLIL::SigSpec s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
{
- log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1);
- if (s.__chunks[0].wire) {
- if (s.__chunks[0].wire->width > 1)
- fprintf(f, " %s[%d]", RTLIL::id2cstr(s.__chunks[0].wire->name), s.__chunks[0].offset);
+ log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1);
+ if (s.chunks()[0].wire) {
+ if (s.chunks()[0].wire->width > 1)
+ fprintf(f, " %s[%d]", RTLIL::id2cstr(s.chunks()[0].wire->name), s.chunks()[0].offset);
else
- fprintf(f, " %s", RTLIL::id2cstr(s.__chunks[0].wire->name));
+ fprintf(f, " %s", RTLIL::id2cstr(s.chunks()[0].wire->name));
} else {
- if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S0)
+ if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S0)
fprintf(f, " %s", neg.c_str());
- else if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S1)
+ else if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S1)
fprintf(f, " %s", pos.c_str());
else
fprintf(f, " %s%d", ncpf.c_str(), nc_counter++);
}
for (auto &sig : port_sigs) {
- for (int i = 0; i < sig.__width; i++) {
- RTLIL::SigSpec s = sig.extract(big_endian ? sig.__width - 1 - i : i, 1);
- log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1);
+ for (int i = 0; i < sig.size(); i++) {
+ RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1);
+ log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1);
print_spice_net(f, s, neg, pos, ncpf, nc_counter);
}
}
}
for (auto &conn : module->connections)
- for (int i = 0; i < conn.first.__width; i++) {
+ for (int i = 0; i < conn.first.size(); i++) {
fprintf(f, "V%d", conn_counter++);
print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter);
print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter);
bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name)
{
sig.optimize();
- if (sig.__chunks.size() != 1 || sig.__chunks[0].wire == NULL)
+ if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL)
return false;
- if (reg_wires.count(sig.__chunks[0].wire->name) == 0)
+ if (reg_wires.count(sig.chunks()[0].wire->name) == 0)
return false;
- reg_name = id(sig.__chunks[0].wire->name);
- if (sig.__width != sig.__chunks[0].wire->width) {
- if (sig.__width == 1)
- reg_name += stringf("[%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset);
+ reg_name = id(sig.chunks()[0].wire->name);
+ if (sig.size() != sig.chunks()[0].wire->width) {
+ if (sig.size() == 1)
+ reg_name += stringf("[%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset);
else
- reg_name += stringf("[%d:%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset + sig.__chunks[0].width - 1,
- sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset);
+ reg_name += stringf("[%d:%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset + sig.chunks()[0].width - 1,
+ sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset);
}
return true;
}
void dump_sigspec(FILE *f, RTLIL::SigSpec &sig)
{
- if (sig.__chunks.size() == 1) {
- dump_sigchunk(f, sig.__chunks[0]);
+ if (sig.chunks().size() == 1) {
+ dump_sigchunk(f, sig.chunks()[0]);
} else {
fprintf(f, "{ ");
- for (auto it = sig.__chunks.rbegin(); it != sig.__chunks.rend(); it++) {
- if (it != sig.__chunks.rbegin())
+ for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) {
+ if (it != sig.chunks().rbegin())
fprintf(f, ", ");
dump_sigchunk(f, *it, true);
}
if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections.count("\\Q") > 0)
{
RTLIL::SigSpec sig = cell->connections["\\Q"];
- if (sig.__width != 1 || sig.is_fully_const())
+ if (sig.size() != 1 || sig.is_fully_const())
goto no_special_reg_name;
sig.optimize();
- RTLIL::Wire *wire = sig.__chunks[0].wire;
+ RTLIL::Wire *wire = sig.chunks()[0].wire;
if (wire->name[0] != '\\')
goto no_special_reg_name;
cell_name = cell_name + "_reg";
if (wire->width != 1)
- cell_name += stringf("[%d]", wire->start_offset + sig.__chunks[0].offset);
+ cell_name += stringf("[%d]", wire->start_offset + sig.chunks()[0].offset);
if (active_module && active_module->count_id(cell_name) > 0)
goto no_special_reg_name;
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe")
{
int width = cell->parameters["\\WIDTH"].as_int();
- int s_width = cell->connections["\\S"].__width;
+ int s_width = cell->connections["\\S"].size();
std::string func_name = cellname(cell);
fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str());
fprintf(f, ",");
first_arg = false;
fprintf(f, "\n%s .%s(", indent.c_str(), id(it->first).c_str());
- if (it->second.__width > 0)
+ if (it->second.size() > 0)
dump_sigspec(f, it->second);
fprintf(f, ")");
}
fprintf(f, "%s" "begin\n", indent.c_str());
for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) {
- if (it->first.__width == 0)
+ if (it->first.size() == 0)
continue;
fprintf(f, "%s ", indent.c_str());
dump_sigspec(f, it->first);
void dump_proc_switch(FILE *f, std::string indent, RTLIL::SwitchRule *sw)
{
- if (sw->signal.__width == 0) {
+ if (sw->signal.size() == 0) {
fprintf(f, "%s" "begin\n", indent.c_str());
for (auto it = sw->cases.begin(); it != sw->cases.end(); it++) {
if ((*it)->compare.size() == 0)
case_body_find_regs(*it2);
for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) {
- for (size_t i = 0; i < it->first.__chunks.size(); i++)
- if (it->first.__chunks[i].wire)
- reg_wires.insert(it->first.__chunks[i].wire->name);
+ for (size_t i = 0; i < it->first.chunks().size(); i++)
+ if (it->first.chunks()[i].wire)
+ reg_wires.insert(it->first.chunks()[i].wire->name);
}
}
case_body_find_regs(&proc->root_case);
for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++)
for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) {
- for (size_t i = 0; i < it2->first.__chunks.size(); i++)
- if (it2->first.__chunks[i].wire)
- reg_wires.insert(it2->first.__chunks[i].wire->name);
+ for (size_t i = 0; i < it2->first.chunks().size(); i++)
+ if (it2->first.chunks()[i].wire)
+ reg_wires.insert(it2->first.chunks()[i].wire->name);
}
return;
}
}
for (auto it = sync->actions.begin(); it != sync->actions.end(); it++) {
- if (it->first.__width == 0)
+ if (it->first.size() == 0)
continue;
fprintf(f, "%s ", indent.c_str());
dump_sigspec(f, it->first);
RTLIL::SigSpec sig = cell->connections["\\Q"];
sig.optimize();
- if (sig.__chunks.size() == 1 && sig.__chunks[0].wire)
- for (int i = 0; i < sig.__chunks[0].width; i++)
- reg_bits.insert(std::pair<RTLIL::Wire*,int>(sig.__chunks[0].wire, sig.__chunks[0].offset+i));
+ if (sig.chunks().size() == 1 && sig.chunks()[0].wire)
+ for (int i = 0; i < sig.chunks()[0].width; i++)
+ reg_bits.insert(std::pair<RTLIL::Wire*,int>(sig.chunks()[0].wire, sig.chunks()[0].offset+i));
}
for (auto &it : module->wires)
{
chunk.offset = 0;
RTLIL::SigSpec sig;
- sig.__chunks.push_back(chunk);
- sig.__width = chunk.width;
+ sig.chunks().push_back(chunk);
+ sig.size() = chunk.width;
if (gen_attributes)
for (auto &attr : that->attributes) {
}
cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.__width);
+ cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
cell->connections["\\A"] = arg;
cell->parameters["\\Y_WIDTH"] = result_width;
// helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed, std::string celltype)
{
- if (width <= sig.__width) {
+ if (width <= sig.size()) {
sig.extend(width, is_signed);
return;
}
chunk.offset = 0;
RTLIL::SigSpec new_sig;
- new_sig.__chunks.push_back(chunk);
- new_sig.__width = chunk.width;
+ new_sig.chunks().push_back(chunk);
+ new_sig.size() = chunk.width;
if (that != NULL)
for (auto &attr : that->attributes) {
}
cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.__width);
+ cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
cell->connections["\\A"] = sig;
cell->parameters["\\Y_WIDTH"] = width;
chunk.offset = 0;
RTLIL::SigSpec sig;
- sig.__chunks.push_back(chunk);
- sig.__width = chunk.width;
+ sig.chunks().push_back(chunk);
+ sig.size() = chunk.width;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.__width);
- cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.__width);
+ cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
+ cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
cell->connections["\\A"] = left;
cell->connections["\\B"] = right;
// helper function for creating RTLIL code for multiplexers
static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
- assert(cond.__width == 1);
+ assert(cond.size() == 1);
std::stringstream sstr;
sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
RTLIL::Wire *wire = new RTLIL::Wire;
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
wire->name = cell->name + "_Y";
- wire->width = left.__width;
+ wire->width = left.size();
current_module->wires[wire->name] = wire;
RTLIL::SigChunk chunk;
chunk.offset = 0;
RTLIL::SigSpec sig;
- sig.__chunks.push_back(chunk);
- sig.__width = chunk.width;
+ sig.chunks().push_back(chunk);
+ sig.size() = chunk.width;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->parameters["\\WIDTH"] = RTLIL::Const(left.__width);
+ cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
cell->connections["\\A"] = right;
cell->connections["\\B"] = left;
// create initial assignments for the temporary signals
if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
subst_rvalue_from = subst_lvalue_from;
- subst_rvalue_to = RTLIL::SigSpec(RTLIL::State::Sx, subst_rvalue_from.__width);
+ subst_rvalue_to = RTLIL::SigSpec(RTLIL::State::Sx, subst_rvalue_from.size());
} else {
addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
}
if (child->type == AST_BLOCK)
processAst(child);
- if (initSyncSignals.__width > 0)
+ if (initSyncSignals.size() > 0)
{
RTLIL::SyncRule *sync = new RTLIL::SyncRule;
sync->type = RTLIL::SyncType::STi;
proc->syncs.push_back(sync);
- assert(init_lvalue.__width == init_rvalue.__width);
+ assert(init_lvalue.size() == init_rvalue.size());
init_lvalue.optimize();
init_rvalue.optimize();
int offset = 0;
- for (size_t i = 0; i < init_lvalue.__chunks.size(); i++) {
- RTLIL::SigSpec lhs = init_lvalue.__chunks[i];
- RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue.__chunks[i].width);
+ for (size_t i = 0; i < init_lvalue.chunks().size(); i++) {
+ RTLIL::SigSpec lhs = init_lvalue.chunks()[i];
+ RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue.chunks()[i].width);
sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
- offset += lhs.__width;
+ offset += lhs.size();
}
}
}
RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
{
sig.optimize();
- for (size_t i = 0; i < sig.__chunks.size(); i++)
+ for (size_t i = 0; i < sig.chunks().size(); i++)
{
- RTLIL::SigChunk &chunk = sig.__chunks[i];
+ RTLIL::SigChunk &chunk = sig.chunks()[i];
if (chunk.wire == NULL)
continue;
// are avoided and the generated $mux cells have a more "natural" size.
void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
{
- if (inSyncRule && initSyncSignals.__width > 0) {
+ if (inSyncRule && initSyncSignals.size() > 0) {
init_lvalue.append(lvalue.extract(initSyncSignals));
init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
lvalue.remove2(initSyncSignals, &rvalue);
}
- assert(lvalue.__width == rvalue.__width);
+ assert(lvalue.size() == rvalue.size());
lvalue.optimize();
rvalue.optimize();
int offset = 0;
- for (size_t i = 0; i < lvalue.__chunks.size(); i++) {
- RTLIL::SigSpec lhs = lvalue.__chunks[i];
- RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue.__chunks[i].width);
- if (inSyncRule && lvalue.__chunks[i].wire && lvalue.__chunks[i].wire->get_bool_attribute("\\nosync"))
- rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.__width);
+ for (size_t i = 0; i < lvalue.chunks().size(); i++) {
+ RTLIL::SigSpec lhs = lvalue.chunks()[i];
+ RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue.chunks()[i].width);
+ if (inSyncRule && lvalue.chunks()[i].wire && lvalue.chunks()[i].wire->get_bool_attribute("\\nosync"))
+ rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
actions.push_back(RTLIL::SigSig(lhs, rhs));
- offset += lhs.__width;
+ offset += lhs.size();
}
}
case AST_ASSIGN_LE:
{
RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
- RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.__width, &subst_rvalue_from, &subst_rvalue_to);
+ RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &subst_rvalue_from, &subst_rvalue_to);
lvalue.replace(subst_lvalue_from, subst_lvalue_to);
if (ast->type == AST_ASSIGN_EQ) {
else if (node->type == AST_BLOCK)
processAst(node);
else
- current_case->compare.push_back(node->genWidthRTLIL(sw->signal.__width, &subst_rvalue_from, &subst_rvalue_to));
+ current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &subst_rvalue_from, &subst_rvalue_to));
}
if (default_case != current_case)
sw->cases.push_back(current_case);
}
RTLIL::SigSpec sig;
- sig.__chunks.push_back(chunk);
- sig.__width = chunk.width;
+ sig.chunks().push_back(chunk);
+ sig.size() = chunk.width;
if (genRTLIL_subst_from && genRTLIL_subst_to)
sig.replace(*genRTLIL_subst_from, *genRTLIL_subst_to);
case AST_TO_SIGNED:
case AST_TO_UNSIGNED: {
RTLIL::SigSpec sig = children[0]->genRTLIL();
- if (sig.__width < width_hint)
+ if (sig.size() < width_hint)
sig.extend_u0(width_hint, sign_hint);
is_signed = sign_hint;
return sig;
// concatenation of signals can be done directly using RTLIL::SigSpec
case AST_CONCAT: {
RTLIL::SigSpec sig;
- sig.__width = 0;
+ sig.size() = 0;
for (auto it = children.begin(); it != children.end(); it++) {
RTLIL::SigSpec s = (*it)->genRTLIL();
- for (size_t i = 0; i < s.__chunks.size(); i++) {
- sig.__chunks.push_back(s.__chunks[i]);
- sig.__width += s.__chunks[i].width;
+ for (size_t i = 0; i < s.chunks().size(); i++) {
+ sig.chunks().push_back(s.chunks()[i]);
+ sig.size() += s.chunks()[i].width;
}
}
- if (sig.__width < width_hint)
+ if (sig.size() < width_hint)
sig.extend_u0(width_hint, false);
return sig;
}
RTLIL::SigSpec sig;
for (int i = 0; i < count; i++)
sig.append(right);
- if (sig.__width < width_hint)
+ if (sig.size() < width_hint)
sig.extend_u0(width_hint, false);
is_signed = false;
return sig;
{
RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
is_signed = children[0]->is_signed;
- int width = arg.__width;
+ int width = arg.size();
if (width_hint > 0) {
width = width_hint;
widthExtend(this, arg, width, is_signed, "$pos");
detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
- int width = std::max(left.__width, right.__width);
+ int width = std::max(left.size(), right.size());
if (width_hint > 0)
width = width_hint;
is_signed = children[0]->is_signed && children[1]->is_signed;
if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
- RTLIL::SigSpec sig = arg.__width > 1 ? uniop2rtlil(this, type_name, std::max(width_hint, 1), arg) : arg;
+ RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, std::max(width_hint, 1), arg) : arg;
return sig;
}
detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL();
- int width = width_hint > 0 ? width_hint : left.__width;
+ int width = width_hint > 0 ? width_hint : left.size();
is_signed = children[0]->is_signed;
return binop2rtlil(this, type_name, width, left, right);
}
detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(right_width, right_signed);
- int width = width_hint > 0 ? width_hint : left.__width;
+ int width = width_hint > 0 ? width_hint : left.size();
is_signed = children[0]->is_signed;
if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
- return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.__width), right);
+ return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
return binop2rtlil(this, "$pow", width, left, right);
}
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
#if 0
- int width = std::max(left.__width, right.__width);
+ int width = std::max(left.size(), right.size());
if (width > width_hint && width_hint > 0)
width = width_hint;
if (width < width_hint) {
if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
width = width_hint;
if (type == AST_MUL)
- width = std::min(left.__width + right.__width, width_hint);
+ width = std::min(left.size() + right.size(), width_hint);
}
#else
- int width = std::max(std::max(left.__width, right.__width), width_hint);
+ int width = std::max(std::max(left.size(), right.size()), width_hint);
#endif
is_signed = children[0]->is_signed && children[1]->is_signed;
return binop2rtlil(this, type_name, width, left, right);
RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
- if (cond.__width > 1)
+ if (cond.size() > 1)
cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
- int width = std::max(val1.__width, val2.__width);
+ int width = std::max(val1.size(), val2.size());
is_signed = children[1]->is_signed && children[2]->is_signed;
widthExtend(this, val1, width, is_signed, "$bu0");
widthExtend(this, val2, width, is_signed, "$bu0");
RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
- if (sig.__width < width_hint)
+ if (sig.size() < width_hint)
sig.extend_u0(width_hint, sign_hint);
return sig;
}
log_assert(children.size() == 2);
RTLIL::SigSpec check = children[0]->genRTLIL();
- log_assert(check.__width == 1);
+ log_assert(check.size() == 1);
RTLIL::SigSpec en = children[1]->genRTLIL();
- log_assert(en.__width == 1);
+ log_assert(en.size() == 1);
std::stringstream sstr;
sstr << "$assert$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
{
if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_AUTOWIRE) {
RTLIL::SigSpec right = children[1]->genRTLIL();
- RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.__width);
+ RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.size());
current_module->connections.push_back(RTLIL::SigSig(left, right));
} else {
RTLIL::SigSpec left = children[0]->genRTLIL();
- RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.__width);
+ RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
current_module->connections.push_back(RTLIL::SigSig(left, right));
}
}
chunk.offset = 0;
chunk.data = *$1;
$$ = new RTLIL::SigSpec;
- $$->__chunks.push_back(chunk);
- $$->__width = chunk.width;
+ $$->chunks().push_back(chunk);
+ $$->size() = chunk.width;
delete $1;
} |
TOK_ID {
chunk.width = current_module->wires[$1]->width;
chunk.offset = 0;
$$ = new RTLIL::SigSpec;
- $$->__chunks.push_back(chunk);
- $$->__width = chunk.width;
+ $$->chunks().push_back(chunk);
+ $$->size() = chunk.width;
free($1);
} |
TOK_ID '[' TOK_INT ']' {
chunk.offset = $3;
chunk.width = 1;
$$ = new RTLIL::SigSpec;
- $$->__chunks.push_back(chunk);
- $$->__width = 1;
+ $$->chunks().push_back(chunk);
+ $$->size() = 1;
free($1);
} |
TOK_ID '[' TOK_INT ':' TOK_INT ']' {
chunk.width = $3 - $5 + 1;
chunk.offset = $5;
$$ = new RTLIL::SigSpec;
- $$->__chunks.push_back(chunk);
- $$->__width = chunk.width;
+ $$->chunks().push_back(chunk);
+ $$->size() = chunk.width;
free($1);
} |
'{' sigspec_list '}' {
sigspec_list:
sigspec_list sigspec {
$$ = new RTLIL::SigSpec;
- for (auto it = $2->__chunks.begin(); it != $2->__chunks.end(); it++) {
- $$->__chunks.push_back(*it);
- $$->__width += it->width;
+ for (auto it = $2->chunks().begin(); it != $2->chunks().end(); it++) {
+ $$->chunks().push_back(*it);
+ $$->size() += it->width;
}
- for (auto it = $1->__chunks.begin(); it != $1->__chunks.end(); it++) {
- $$->__chunks.push_back(*it);
- $$->__width += it->width;
+ for (auto it = $1->chunks().begin(); it != $1->chunks().end(); it++) {
+ $$->chunks().push_back(*it);
+ $$->size() += it->width;
}
delete $1;
delete $2;
preset_sig = parse_func_expr(module, child->value.c_str());
}
- if (clk_sig.__width == 0 || data_sig.__width == 0)
+ if (clk_sig.size() == 0 || data_sig.size() == 0)
log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", RTLIL::id2cstr(module->name));
for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
cell->connections["\\C"] = clk_sig;
module->add(cell);
- if (clear_sig.__width == 0 && preset_sig.__width == 0) {
+ if (clear_sig.size() == 0 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
}
- if (clear_sig.__width == 1 && preset_sig.__width == 0) {
+ if (clear_sig.size() == 1 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
cell->connections["\\R"] = clear_sig;
}
- if (clear_sig.__width == 0 && preset_sig.__width == 1) {
+ if (clear_sig.size() == 0 && preset_sig.size() == 1) {
cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
cell->connections["\\R"] = preset_sig;
}
- if (clear_sig.__width == 1 && preset_sig.__width == 1) {
+ if (clear_sig.size() == 1 && preset_sig.size() == 1) {
cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
cell->connections["\\S"] = preset_sig;
cell->connections["\\R"] = clear_sig;
preset_sig = parse_func_expr(module, child->value.c_str());
}
- if (enable_sig.__width == 0 || data_sig.__width == 0)
+ if (enable_sig.size() == 0 || data_sig.size() == 0)
log_error("Latch cell %s has no data_in and/or enable attribute.\n", RTLIL::id2cstr(module->name));
for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
cell->connections["\\Y"] = iqn_sig;
module->add(cell);
- if (clear_sig.__width == 1)
+ if (clear_sig.size() == 1)
{
RTLIL::SigSpec clear_negative = clear_sig;
RTLIL::SigSpec clear_enable = clear_sig;
module->add(enable_gate);
}
- if (preset_sig.__width == 1)
+ if (preset_sig.size() == 1)
{
RTLIL::SigSpec preset_positive = preset_sig;
RTLIL::SigSpec preset_enable = preset_sig;
BitPatternPool(RTLIL::SigSpec sig)
{
- width = sig.__width;
+ width = sig.size();
if (width > 0) {
std::vector<RTLIL::State> pattern(width);
sig.optimize();
for (int i = 0; i < width; i++) {
RTLIL::SigSpec s = sig.extract(i, 1);
s.optimize();
- assert(s.__chunks.size() == 1);
- if (s.__chunks[0].wire == NULL && s.__chunks[0].data.bits[0] <= RTLIL::State::S1)
- pattern[i] = s.__chunks[0].data.bits[0];
+ assert(s.chunks().size() == 1);
+ if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1)
+ pattern[i] = s.chunks()[0].data.bits[0];
else
pattern[i] = RTLIL::State::Sa;
}
{
sig.optimize();
assert(sig.is_fully_const());
- assert(sig.__chunks.size() == 1);
- bits_t bits = sig.__chunks[0].data.bits;
+ assert(sig.chunks().size() == 1);
+ bits_t bits = sig.chunks()[0].data.bits;
for (auto &b : bits)
if (b > RTLIL::State::S1)
b = RTLIL::State::Sa;
#ifndef NDEBUG
RTLIL::SigSpec current_val = values_map(sig);
current_val.expand();
- for (size_t i = 0; i < current_val.__chunks.size(); i++) {
- RTLIL::SigChunk &chunk = current_val.__chunks[i];
+ for (size_t i = 0; i < current_val.chunks().size(); i++) {
+ RTLIL::SigChunk &chunk = current_val.chunks()[i];
assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]);
}
#endif
int count_maybe_set_s_bits = 0;
int count_set_s_bits = 0;
- for (int i = 0; i < sig_s.__width; i++)
+ for (int i = 0; i < sig_s.size(); i++)
{
RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
- RTLIL::SigSpec b_slice = sig_b.extract(sig_y.__width*i, sig_y.__width);
+ RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());
if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)
y_candidates.push_back(b_slice);
}
else
{
- if (sig_a.__width > 0 && !eval(sig_a, undef, cell))
+ if (sig_a.size() > 0 && !eval(sig_a, undef, cell))
return false;
- if (sig_b.__width > 0 && !eval(sig_b, undef, cell))
+ if (sig_b.size() > 0 && !eval(sig_b, undef, cell))
return false;
set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const()));
}
if (sig.is_fully_const())
return true;
- for (size_t i = 0; i < sig.__chunks.size(); i++)
- if (sig.__chunks[i].wire != NULL)
- undef.append(sig.__chunks[i]);
+ for (size_t i = 0; i < sig.chunks().size(); i++)
+ if (sig.chunks()[i].wire != NULL)
+ undef.append(sig.chunks()[i]);
return false;
}
{
if (cell->connections.count(name) == 0)
error(__LINE__);
- if (cell->connections.at(name).__width != width)
+ if (cell->connections.at(name).size() != width)
error(__LINE__);
expected_ports.insert(name);
}
char portname[3] = { '\\', *p, 0 };
if (cell->connections.count(portname) == 0)
error(__LINE__);
- if (cell->connections.at(portname).__width != 1)
+ if (cell->connections.at(portname).size() != 1)
error(__LINE__);
}
}
for (auto &it : connections) {
- assert(it.first.__width == it.second.__width);
+ assert(it.first.size() == it.second.size());
it.first.check();
it.second.check();
}
RTLIL::Module *mod;
void operator()(RTLIL::SigSpec &sig)
{
- for (auto &c : sig.__chunks)
+ for (auto &c : sig.chunks())
if (c.wire != NULL)
c.wire = mod->wires.at(c.wire->name);
}
cell->name = name; \
cell->type = _type; \
cell->parameters["\\A_SIGNED"] = is_signed; \
- cell->parameters["\\A_WIDTH"] = sig_a.__width; \
- cell->parameters["\\Y_WIDTH"] = sig_y.__width; \
+ cell->parameters["\\A_WIDTH"] = sig_a.size(); \
+ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
cell->connections["\\A"] = sig_a; \
cell->connections["\\Y"] = sig_y; \
add(cell); \
add ## _func(name, sig_a, sig_y, is_signed); \
return sig_y; \
}
-DEF_METHOD(Not, sig_a.__width, "$not")
-DEF_METHOD(Pos, sig_a.__width, "$pos")
-DEF_METHOD(Bu0, sig_a.__width, "$bu0")
-DEF_METHOD(Neg, sig_a.__width, "$neg")
+DEF_METHOD(Not, sig_a.size(), "$not")
+DEF_METHOD(Pos, sig_a.size(), "$pos")
+DEF_METHOD(Bu0, sig_a.size(), "$bu0")
+DEF_METHOD(Neg, sig_a.size(), "$neg")
DEF_METHOD(ReduceAnd, 1, "$reduce_and")
DEF_METHOD(ReduceOr, 1, "$reduce_or")
DEF_METHOD(ReduceXor, 1, "$reduce_xor")
cell->type = _type; \
cell->parameters["\\A_SIGNED"] = is_signed; \
cell->parameters["\\B_SIGNED"] = is_signed; \
- cell->parameters["\\A_WIDTH"] = sig_a.__width; \
- cell->parameters["\\B_WIDTH"] = sig_b.__width; \
- cell->parameters["\\Y_WIDTH"] = sig_y.__width; \
+ cell->parameters["\\A_WIDTH"] = sig_a.size(); \
+ cell->parameters["\\B_WIDTH"] = sig_b.size(); \
+ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
cell->connections["\\A"] = sig_a; \
cell->connections["\\B"] = sig_b; \
cell->connections["\\Y"] = sig_y; \
add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
return sig_y; \
}
-DEF_METHOD(And, std::max(sig_a.__width, sig_b.__width), "$and")
-DEF_METHOD(Or, std::max(sig_a.__width, sig_b.__width), "$or")
-DEF_METHOD(Xor, std::max(sig_a.__width, sig_b.__width), "$xor")
-DEF_METHOD(Xnor, std::max(sig_a.__width, sig_b.__width), "$xnor")
-DEF_METHOD(Shl, sig_a.__width, "$shl")
-DEF_METHOD(Shr, sig_a.__width, "$shr")
-DEF_METHOD(Sshl, sig_a.__width, "$sshl")
-DEF_METHOD(Sshr, sig_a.__width, "$sshr")
+DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
+DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
+DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
+DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
+DEF_METHOD(Shl, sig_a.size(), "$shl")
+DEF_METHOD(Shr, sig_a.size(), "$shr")
+DEF_METHOD(Sshl, sig_a.size(), "$sshl")
+DEF_METHOD(Sshr, sig_a.size(), "$sshr")
DEF_METHOD(Lt, 1, "$lt")
DEF_METHOD(Le, 1, "$le")
DEF_METHOD(Eq, 1, "$eq")
DEF_METHOD(Nex, 1, "$nex")
DEF_METHOD(Ge, 1, "$ge")
DEF_METHOD(Gt, 1, "$gt")
-DEF_METHOD(Add, std::max(sig_a.__width, sig_b.__width), "$add")
-DEF_METHOD(Sub, std::max(sig_a.__width, sig_b.__width), "$sub")
-DEF_METHOD(Mul, std::max(sig_a.__width, sig_b.__width), "$mul")
-DEF_METHOD(Div, std::max(sig_a.__width, sig_b.__width), "$div")
-DEF_METHOD(Mod, std::max(sig_a.__width, sig_b.__width), "$mod")
+DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
+DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
+DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
+DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
+DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
DEF_METHOD(LogicAnd, 1, "$logic_and")
DEF_METHOD(LogicOr, 1, "$logic_or")
#undef DEF_METHOD
RTLIL::Cell *cell = new RTLIL::Cell; \
cell->name = name; \
cell->type = _type; \
- cell->parameters["\\WIDTH"] = sig_a.__width; \
- cell->parameters["\\WIDTH"] = sig_b.__width; \
- if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.__width; \
+ cell->parameters["\\WIDTH"] = sig_a.size(); \
+ cell->parameters["\\WIDTH"] = sig_b.size(); \
+ if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
cell->connections["\\A"] = sig_a; \
cell->connections["\\B"] = sig_b; \
cell->connections["\\S"] = sig_s; \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
- RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.__width); \
+ RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
return sig_y; \
}
cell->type = "$pow";
cell->parameters["\\A_SIGNED"] = a_signed;
cell->parameters["\\B_SIGNED"] = b_signed;
- cell->parameters["\\A_WIDTH"] = sig_a.__width;
- cell->parameters["\\B_WIDTH"] = sig_b.__width;
- cell->parameters["\\Y_WIDTH"] = sig_y.__width;
+ cell->parameters["\\A_WIDTH"] = sig_a.size();
+ cell->parameters["\\B_WIDTH"] = sig_b.size();
+ cell->parameters["\\Y_WIDTH"] = sig_y.size();
cell->connections["\\A"] = sig_a;
cell->connections["\\B"] = sig_b;
cell->connections["\\Y"] = sig_y;
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = "$slice";
- cell->parameters["\\A_WIDTH"] = sig_a.__width;
- cell->parameters["\\Y_WIDTH"] = sig_y.__width;
+ cell->parameters["\\A_WIDTH"] = sig_a.size();
+ cell->parameters["\\Y_WIDTH"] = sig_y.size();
cell->parameters["\\OFFSET"] = offset;
cell->connections["\\A"] = sig_a;
cell->connections["\\Y"] = sig_y;
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = "$concat";
- cell->parameters["\\A_WIDTH"] = sig_a.__width;
- cell->parameters["\\B_WIDTH"] = sig_b.__width;
+ cell->parameters["\\A_WIDTH"] = sig_a.size();
+ cell->parameters["\\B_WIDTH"] = sig_b.size();
cell->connections["\\A"] = sig_a;
cell->connections["\\B"] = sig_b;
cell->connections["\\Y"] = sig_y;
cell->name = name;
cell->type = "$lut";
cell->parameters["\\LUT"] = lut;
- cell->parameters["\\WIDTH"] = sig_i.__width;
+ cell->parameters["\\WIDTH"] = sig_i.size();
cell->connections["\\I"] = sig_i;
cell->connections["\\O"] = sig_o;
add(cell);
cell->type = "$sr";
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
- cell->parameters["\\WIDTH"] = sig_q.__width;
+ cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\SET"] = sig_set;
cell->connections["\\CLR"] = sig_clr;
cell->connections["\\Q"] = sig_q;
cell->name = name;
cell->type = "$dff";
cell->parameters["\\CLK_POLARITY"] = clk_polarity;
- cell->parameters["\\WIDTH"] = sig_q.__width;
+ cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\CLK"] = sig_clk;
cell->connections["\\D"] = sig_d;
cell->connections["\\Q"] = sig_q;
cell->parameters["\\CLK_POLARITY"] = clk_polarity;
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
- cell->parameters["\\WIDTH"] = sig_q.__width;
+ cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\CLK"] = sig_clk;
cell->connections["\\SET"] = sig_set;
cell->connections["\\CLR"] = sig_clr;
cell->parameters["\\CLK_POLARITY"] = clk_polarity;
cell->parameters["\\ARST_POLARITY"] = arst_polarity;
cell->parameters["\\ARST_VALUE"] = arst_value;
- cell->parameters["\\WIDTH"] = sig_q.__width;
+ cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\CLK"] = sig_clk;
cell->connections["\\ARST"] = sig_arst;
cell->connections["\\D"] = sig_d;
cell->name = name;
cell->type = "$dlatch";
cell->parameters["\\EN_POLARITY"] = en_polarity;
- cell->parameters["\\WIDTH"] = sig_q.__width;
+ cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\EN"] = sig_en;
cell->connections["\\D"] = sig_d;
cell->connections["\\Q"] = sig_q;
cell->parameters["\\EN_POLARITY"] = en_polarity;
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
- cell->parameters["\\WIDTH"] = sig_q.__width;
+ cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\EN"] = sig_en;
cell->connections["\\SET"] = sig_set;
cell->connections["\\CLR"] = sig_clr;
};
inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
- assert(sig.__width == 1 && sig.__chunks.size() == 1);
- *this = SigBit(sig.__chunks[0]);
+ assert(sig.size() == 1 && sig.chunks().size() == 1);
+ *this = SigBit(sig.chunks()[0]);
}
struct RTLIL::CaseRule {
sig.expand();
std::vector<int> vec;
- vec.reserve(sig.__chunks.size());
+ vec.reserve(sig.chunks().size());
- for (auto &c : sig.__chunks)
+ for (auto &c : sig.chunks())
if (c.wire == NULL) {
RTLIL::State bit = c.data.bits.at(0);
if (model_undef && dup_undef && bit == RTLIL::State::Sx)
if (timestep_rhs < 0)
timestep_rhs = timestep_lhs;
- assert(lhs.__width == rhs.__width);
+ assert(lhs.size() == rhs.size());
std::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);
std::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);
std::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);
std::vector<int> eq_bits;
- for (int i = 0; i < lhs.__width; i++)
+ for (int i = 0; i < lhs.size(); i++)
eq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),
ez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));
return ez->expression(ezSAT::OpAnd, eq_bits);
only_first_one.at(0) = ez->TRUE;
div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
} else {
- div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").__width, ez->TRUE);
+ div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").size(), ez->TRUE);
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
}
} else {
- int copy_a_bits = std::min(cell->connections.at("\\A").__width, cell->connections.at("\\B").__width);
+ int copy_a_bits = std::min(cell->connections.at("\\A").size(), cell->connections.at("\\B").size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
{
RTLIL::SigSpec a = cell->connections.at("\\A");
RTLIL::SigSpec y = cell->connections.at("\\Y");
- ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.__width), y, timestep));
+ ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep));
return true;
}
void add(RTLIL::SigSpec sig)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
void del(RTLIL::SigSpec sig)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
{
from.expand();
to.expand();
- assert(from.__chunks.size() == to.__chunks.size());
- for (size_t i = 0; i < from.__chunks.size(); i++) {
- bitDef_t bit_from(from.__chunks[i].wire, from.__chunks[i].offset);
- bitDef_t bit_to(to.__chunks[i].wire, to.__chunks[i].offset);
+ assert(from.chunks().size() == to.chunks().size());
+ for (size_t i = 0; i < from.chunks().size(); i++) {
+ bitDef_t bit_from(from.chunks()[i].wire, from.chunks()[i].offset);
+ bitDef_t bit_to(to.chunks()[i].wire, to.chunks()[i].offset);
if (bit_from.first == NULL || bit_to.first == NULL)
continue;
if (bits.count(bit_from) > 0)
{
RTLIL::SigSpec result;
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
bitDef_t bit(c.wire, c.offset);
{
RTLIL::SigSpec result;
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
bitDef_t bit(c.wire, c.offset);
bool check_any(RTLIL::SigSpec sig)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
bitDef_t bit(c.wire, c.offset);
bool check_all(RTLIL::SigSpec sig)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
bitDef_t bit(c.wire, c.offset);
void insert(RTLIL::SigSpec sig, T data)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
void insert(RTLIL::SigSpec sig, const std::set<T> &data)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
void erase(RTLIL::SigSpec sig)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
void erase(RTLIL::SigSpec sig, T data)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
void erase(RTLIL::SigSpec sig, const std::set<T> &data)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
void find(RTLIL::SigSpec sig, std::set<T> &result)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
bool has(RTLIL::SigSpec sig)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
from.expand();
to.expand();
- assert(from.__chunks.size() == to.__chunks.size());
- for (size_t i = 0; i < from.__chunks.size(); i++)
+ assert(from.chunks().size() == to.chunks().size());
+ for (size_t i = 0; i < from.chunks().size(); i++)
{
- RTLIL::SigChunk &cf = from.__chunks[i];
- RTLIL::SigChunk &ct = to.__chunks[i];
+ RTLIL::SigChunk &cf = from.chunks()[i];
+ RTLIL::SigChunk &ct = to.chunks()[i];
if (cf.wire == NULL)
continue;
void add(RTLIL::SigSpec sig)
{
sig.expand();
- for (size_t i = 0; i < sig.__chunks.size(); i++)
+ for (size_t i = 0; i < sig.chunks().size(); i++)
{
- RTLIL::SigChunk &c = sig.__chunks[i];
+ RTLIL::SigChunk &c = sig.chunks()[i];
if (c.wire != NULL) {
register_bit(c);
set_bit(c, c);
void del(RTLIL::SigSpec sig)
{
sig.expand();
- for (auto &c : sig.__chunks)
+ for (auto &c : sig.chunks())
unregister_bit(c);
}
void apply(RTLIL::SigSpec &sig) const
{
sig.expand();
- for (auto &c : sig.__chunks)
+ for (auto &c : sig.chunks())
map_bit(c);
sig.optimize();
}
static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1)
{
- assert(sig.__width == 1);
- assert(sig.__chunks.size() == 1);
+ assert(sig.size() == 1);
+ assert(sig.chunks().size() == 1);
assign_map.apply(sig);
{
assign_map.apply(sig);
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire != NULL && signal_map.count(c) > 0)
signal_list[signal_map[c]].is_port = true;
}
RTLIL::SigSpec sig_q = cell->connections["\\Q"];
if (keepff)
- for (auto &c : sig_q.__chunks)
+ for (auto &c : sig_q.chunks())
if (c.wire != NULL)
c.wire->attributes["\\keep"] = 1;
for (auto &edge_it : edges) {
int id2 = edge_it.first;
- RTLIL::Wire *w1 = signal_list[id1].sig.__chunks[0].wire;
- RTLIL::Wire *w2 = signal_list[id2].sig.__chunks[0].wire;
+ RTLIL::Wire *w1 = signal_list[id1].sig.chunks()[0].wire;
+ RTLIL::Wire *w2 = signal_list[id2].sig.chunks()[0].wire;
if (w1 != NULL)
continue;
else if (w2 == NULL)
clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1));
}
- if (dff_mode && clk_sig.__width == 0)
+ if (dff_mode && clk_sig.size() == 0)
{
int best_dff_counter = 0;
std::map<std::pair<bool, RTLIL::SigSpec>, int> dff_counters;
}
if (dff_mode || !clk_str.empty()) {
- if (clk_sig.__width == 0)
+ if (clk_sig.size() == 0)
log("No (matching) clock domain found. Not extracting any FF cells.\n");
else
log("Found (matching) %s clock domain: %s\n", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
}
- if (clk_sig.__width != 0)
+ if (clk_sig.size() != 0)
mark_port(clk_sig);
std::vector<RTLIL::Cell*> cells;
fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.sig));
for (auto &si : signal_list) {
- assert(si.sig.__width == 1 && si.sig.__chunks.size() == 1);
- if (si.sig.__chunks[0].wire == NULL) {
+ assert(si.sig.size() == 1 && si.sig.chunks().size() == 1);
+ if (si.sig.chunks()[0].wire == NULL) {
fprintf(f, ".names n%d\n", si.id);
- if (si.sig.__chunks[0].data.bits[0] == RTLIL::State::S1)
+ if (si.sig.chunks()[0].data.bits[0] == RTLIL::State::S1)
fprintf(f, "1\n");
}
}
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\ZERO" || c->type == "\\ONE") {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]);
+ conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
module->connections.push_back(conn);
continue;
}
if (c->type == "\\BUF") {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]);
- conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]);
+ conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]);
+ conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]);
module->connections.push_back(conn);
continue;
}
RTLIL::Cell *cell = new RTLIL::Cell;
cell->type = "$_INV_";
cell->name = remap_name(c->name);
- cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]);
- cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]);
+ cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]);
+ cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]);
module->cells[cell->name] = cell;
design->select(module, cell);
continue;
RTLIL::Cell *cell = new RTLIL::Cell;
cell->type = "$_" + c->type.substr(1) + "_";
cell->name = remap_name(c->name);
- cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]);
- cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].__chunks[0].wire->name)]);
- cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]);
+ cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]);
+ cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]);
+ cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]);
module->cells[cell->name] = cell;
design->select(module, cell);
continue;
RTLIL::Cell *cell = new RTLIL::Cell;
cell->type = "$_MUX_";
cell->name = remap_name(c->name);
- cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]);
- cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].__chunks[0].wire->name)]);
- cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].__chunks[0].wire->name)]);
- cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]);
+ cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]);
+ cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]);
+ cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks()[0].wire->name)]);
+ cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]);
module->cells[cell->name] = cell;
design->select(module, cell);
continue;
}
if (c->type == "\\DFF") {
- log_assert(clk_sig.__width == 1);
+ log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell = new RTLIL::Cell;
cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_";
cell->name = remap_name(c->name);
- cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].__chunks[0].wire->name)]);
- cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].__chunks[0].wire->name)]);
+ cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]);
+ cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]);
cell->connections["\\C"] = clk_sig;
module->cells[cell->name] = cell;
design->select(module, cell);
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\_const0_" || c->type == "\\_const1_") {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.__chunks[0].wire->name)]);
+ conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.chunks()[0].wire->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
module->connections.push_back(conn);
continue;
}
if (c->type == "\\_dff_") {
- log_assert(clk_sig.__width == 1);
+ log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell = new RTLIL::Cell;
cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_";
cell->name = remap_name(c->name);
- cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].__chunks[0].wire->name)]);
- cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].__chunks[0].wire->name)]);
+ cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]);
+ cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]);
cell->connections["\\C"] = clk_sig;
module->cells[cell->name] = cell;
design->select(module, cell);
cell->name = remap_name(c->name);
for (auto &conn : c->connections) {
RTLIL::SigSpec newsig;
- for (auto &c : conn.second.__chunks) {
+ for (auto &c : conn.second.chunks()) {
if (c.width == 0)
continue;
assert(c.width == 1);
for (auto conn : mapped_mod->connections) {
if (!conn.first.is_fully_const())
- conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.__chunks[0].wire->name)]);
+ conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks()[0].wire->name)]);
if (!conn.second.is_fully_const())
- conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.__chunks[0].wire->name)]);
+ conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks()[0].wire->name)]);
module->connections.push_back(conn);
}
}
input_sig.append(wire);
}
- output_sig = input_sig.extract(input_sig.__width-1, 1);
- input_sig = input_sig.extract(0, input_sig.__width-1);
+ output_sig = input_sig.extract(input_sig.size()-1, 1);
+ input_sig = input_sig.extract(0, input_sig.size()-1);
- if (input_sig.__width == 0) {
+ if (input_sig.size() == 0) {
RTLIL::State state = RTLIL::State::Sa;
while (1) {
if (!read_next_line(buffer, buffer_size, line_count, f))
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$lut";
- cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.__width);
- cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.__width);
+ cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
+ cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->connections["\\I"] = input_sig;
cell->connections["\\O"] = output_sig;
lutptr = &cell->parameters.at("\\LUT");
{
CellTypes ct(design);
- RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.__width);
+ RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
for (auto &it : module->cells)
for (auto &port : it.second->connections)
continue;
int inner_width = cell->parameters.at(decl.widthparam).as_int();
- int outer_width = conn.second.__width;
+ int outer_width = conn.second.size();
bool is_signed = decl.signparam.empty() ? decl.is_signed : cell->parameters.at(decl.signparam).as_bool();
if (inner_width >= outer_width)
int extend_width = 0;
RTLIL::SigBit extend_bit = is_signed ? sigbits[i] : RTLIL::SigBit(RTLIL::State::S0);
- while (extend_width < extend_sig.__width && i + extend_width + 1 < sigbits.size() &&
+ while (extend_width < extend_sig.size() && i + extend_width + 1 < sigbits.size() &&
sigbits[i + extend_width + 1] == extend_bit) extend_width++;
if (extend_width == 0)
continue;
- if (old_sig.__width == 0)
+ if (old_sig.size() == 0)
old_sig = conn.second;
conn.second.replace(i+1, extend_sig.extract(0, extend_width));
i += extend_width;
}
- if (old_sig.__width)
+ if (old_sig.size())
log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name),
RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second));
}
void operator()(RTLIL::SigSpec &sig) {
sig.optimize();
- for (auto &c : sig.__chunks)
+ for (auto &c : sig.chunks())
if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
c.wire = module->addWire(NEW_ID, c.width);
c.offset = 0;
{
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = NEW_ID;
- wire->width = p.second.__width;
+ wire->width = p.second.size();
mod_it.second->add(wire);
if (ct.cell_output(c.second->type, p.first)) {
nextsig.sort_and_unify();
sig = prevsig.extract(nextsig);
- for (auto &chunk : sig.__chunks)
+ for (auto &chunk : sig.chunks())
if (chunk.wire != NULL)
sel.selected_members[module->name].insert(chunk.wire->name);
}
include_match:
is_input = mode == 'x' || ct.cell_input(cell.second->type, conn.first);
is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first);
- for (auto &chunk : conn.second.__chunks)
+ for (auto &chunk : conn.second.chunks())
if (chunk.wire != NULL) {
if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && lhs.selected_members[mod->name].count(cell.first) == 0)
if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input))
void operator()(RTLIL::SigSpec &sig)
{
sig.expand();
- for (auto &c : sig.__chunks)
+ for (auto &c : sig.chunks())
if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1)
c.data.bits.at(0) = next_bit();
sig.optimize();
undriven_signals.del(sigmap(conn.second));
RTLIL::SigSpec sig = undriven_signals.export_all();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
RTLIL::SigSpec bits;
for (int i = 0; i < c.width; i++)
bits.append(next_bit());
std::string nextColor(RTLIL::SigSpec sig, std::string defaultColor)
{
sig.sort_and_unify();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire != NULL)
for (auto &s : color_selections)
if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0)
{
sig.optimize();
- if (sig.__chunks.size() == 0) {
+ if (sig.chunks().size() == 0) {
fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count);
return stringf("v%d", single_idx_count++);
}
- if (sig.__chunks.size() == 1) {
- RTLIL::SigChunk &c = sig.__chunks[0];
+ if (sig.chunks().size() == 1) {
+ RTLIL::SigChunk &c = sig.chunks()[0];
if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
if (!range_check || c.wire->width == c.width)
return stringf("n%d", id2num(c.wire->name));
{
std::string label_string;
sig.optimize();
- int pos = sig.__width-1;
+ int pos = sig.size()-1;
int idx = single_idx_count++;
- for (int i = int(sig.__chunks.size())-1; i >= 0; i--) {
- RTLIL::SigChunk &c = sig.__chunks[i];
+ for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
+ RTLIL::SigChunk &c = sig.chunks()[i];
net = gen_signode_simple(c, false);
assert(!net.empty());
if (driver) {
if (!port.empty()) {
currentColor = xorshift32(currentColor);
if (driver)
- code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.__width).c_str());
+ code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
else
- code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.__width).c_str());
+ code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
}
if (node != NULL)
*node = stringf("x%d", idx);
net_conn_map[net].in.insert(port);
else
net_conn_map[net].out.insert(port);
- net_conn_map[net].bits = sig.__width;
+ net_conn_map[net].bits = sig.size();
net_conn_map[net].color = nextColor(sig, net_conn_map[net].color);
}
if (node != NULL)
code += gen_portbox("", sig, false, &node);
fprintf(f, "%s", code.c_str());
net_conn_map[node].out.insert(stringf("p%d", pidx));
- net_conn_map[node].bits = sig.__width;
+ net_conn_map[node].bits = sig.size();
net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
}
code += gen_portbox("", sig, true, &node);
fprintf(f, "%s", code.c_str());
net_conn_map[node].in.insert(stringf("p%d", pidx));
- net_conn_map[node].bits = sig.__width;
+ net_conn_map[node].bits = sig.size();
net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
}
for (auto &conn : module->connections)
{
bool found_lhs_wire = false;
- for (auto &c : conn.first.__chunks) {
+ for (auto &c : conn.first.chunks()) {
if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
found_lhs_wire = true;
}
bool found_rhs_wire = false;
- for (auto &c : conn.second.__chunks) {
+ for (auto &c : conn.second.chunks()) {
if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
found_rhs_wire = true;
}
if (left_node[0] == 'x' && right_node[0] == 'x') {
currentColor = xorshift32(currentColor);
- fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.__width).c_str());
+ fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.size()).c_str());
} else {
- net_conn_map[right_node].bits = conn.first.__width;
+ net_conn_map[right_node].bits = conn.first.size();
net_conn_map[right_node].color = nextColor(conn, net_conn_map[right_node].color);
- net_conn_map[left_node].bits = conn.first.__width;
+ net_conn_map[left_node].bits = conn.first.size();
net_conn_map[left_node].color = nextColor(conn, net_conn_map[left_node].color);
if (left_node[0] == 'x') {
net_conn_map[right_node].in.insert(left_node);
RTLIL::SigSpec get_sliced_signal(RTLIL::SigSpec sig)
{
- if (sig.__width == 0 || sig.is_fully_const())
+ if (sig.size() == 0 || sig.is_fully_const())
return sig;
if (sliced_signals_cache.count(sig))
RTLIL::SigSpec new_sig = sig;
- if (sig_a.__width != sig.__width) {
+ if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$slice";
cell->parameters["\\OFFSET"] = offset;
- cell->parameters["\\A_WIDTH"] = sig_a.__width;
- cell->parameters["\\Y_WIDTH"] = sig.__width;
+ cell->parameters["\\A_WIDTH"] = sig_a.size();
+ cell->parameters["\\Y_WIDTH"] = sig.size();
cell->connections["\\A"] = sig_a;
- cell->connections["\\Y"] = module->addWire(NEW_ID, sig.__width);
+ cell->connections["\\Y"] = module->addWire(NEW_ID, sig.size());
new_sig = cell->connections["\\Y"];
module->add(cell);
}
RTLIL::SigSpec get_spliced_signal(RTLIL::SigSpec sig)
{
- if (sig.__width == 0 || sig.is_fully_const())
+ if (sig.size() == 0 || sig.is_fully_const())
return sig;
if (spliced_signals_cache.count(sig))
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$concat";
- cell->parameters["\\A_WIDTH"] = new_sig.__width;
- cell->parameters["\\B_WIDTH"] = sig2.__width;
+ cell->parameters["\\A_WIDTH"] = new_sig.size();
+ cell->parameters["\\B_WIDTH"] = sig2.size();
cell->connections["\\A"] = new_sig;
cell->connections["\\B"] = sig2;
- cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.__width + sig2.__width);
+ cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size());
new_sig = cell->connections["\\Y"];
module->add(cell);
}
void operator()(RTLIL::SigSpec &sig)
{
sig.expand();
- for (auto &c : sig.__chunks)
+ for (auto &c : sig.chunks())
if (splitmap.count(c.wire) > 0)
c = splitmap.at(c.wire).at(c.offset);
sig.optimize();
continue;
RTLIL::SigSpec sig = p.second.optimized();
- for (auto &chunk : sig.__chunks) {
+ for (auto &chunk : sig.chunks()) {
if (chunk.wire == NULL)
continue;
if (chunk.wire->port_id == 0 || flag_ports) {
RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]);
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
return false;
- for (int i = 0; i < sig_b.__width; i += sig_a.__width)
- if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.__width), recursion_monitor))
+ for (int i = 0; i < sig_b.size(); i += sig_a.size())
+ if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.size()), recursion_monitor))
return false;
muxtree_cells.insert(cellport.first);
}
bool is_cell_merge_candidate(RTLIL::Cell *cell)
{
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
- if (cell->connections.at("\\A").__width < 2)
+ if (cell->connections.at("\\A").size() < 2)
return true;
RTLIL::SigSpec new_signals;
new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"]));
new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"]));
- if (new_signals.__width > 3)
+ if (new_signals.size() > 3)
return false;
if (cell->connections.count("\\Y") > 0) {
new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"]));
}
- if (new_signals.__width > 2)
+ if (new_signals.size() > 2)
return false;
return true;
std::vector<RTLIL::Const> truth_tab;
- for (int i = 0; i < (1 << input_sig.__width); i++) {
- RTLIL::Const in_val(i, input_sig.__width);
+ for (int i = 0; i < (1 << input_sig.size()); i++) {
+ RTLIL::Const in_val(i, input_sig.size());
RTLIL::SigSpec A, B, S;
if (cell->connections.count("\\A") > 0)
A = assign_map(cell->connections["\\A"]);
FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell);
- fsm_data.num_inputs += input_sig.__width;
+ fsm_data.num_inputs += input_sig.size();
fsm_cell->connections["\\CTRL_IN"].append(input_sig);
- fsm_data.num_outputs += output_sig.__width;
+ fsm_data.num_outputs += output_sig.size();
fsm_cell->connections["\\CTRL_OUT"].append(output_sig);
std::vector<FsmData::transition_t> new_transition_table;
for (auto &tr : fsm_data.transition_table) {
- for (int i = 0; i < (1 << input_sig.__width); i++) {
+ for (int i = 0; i < (1 << input_sig.size()); i++) {
FsmData::transition_t new_tr = tr;
- RTLIL::Const in_val(i, input_sig.__width);
+ RTLIL::Const in_val(i, input_sig.size());
RTLIL::Const out_val = truth_tab[i];
RTLIL::SigSpec ctrl_in = new_tr.ctrl_in;
RTLIL::SigSpec ctrl_out = new_tr.ctrl_out;
static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
{
- sig.extend(dff_out.__width, false);
+ sig.extend(dff_out.size(), false);
if (sig == dff_out)
return true;
assign_map.apply(sig);
if (sig.is_fully_const()) {
sig.optimize();
- assert(sig.__chunks.size() == 1);
- if (states.count(sig.__chunks[0].data) == 0) {
+ assert(sig.chunks().size() == 1);
+ if (states.count(sig.chunks()[0].data) == 0) {
log(" found state code: %s\n", log_signal(sig));
- states[sig.__chunks[0].data] = -1;
+ states[sig.chunks()[0].data] = -1;
}
return true;
}
break;
log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state));
} while (0);
- if (ctrl.extract(sig_s).__width == 0) {
+ if (ctrl.extract(sig_s).size() == 0) {
log(" found ctrl input: %s\n", log_signal(sig_s));
ctrl.append(sig_s);
}
if (!find_states(sig_a, dff_out, ctrl, states))
return false;
- for (int i = 0; i < sig_b.__width/sig_a.__width; i++) {
- if (!find_states(sig_b.extract(i*sig_a.__width, sig_a.__width), dff_out, ctrl, states))
+ for (int i = 0; i < sig_b.size()/sig_a.size(); i++) {
+ if (!find_states(sig_b.extract(i*sig_a.size(), sig_a.size()), dff_out, ctrl, states))
return false;
}
}
static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec())
{
- if (dont_care.__width > 0) {
+ if (dont_care.size() > 0) {
sig.expand();
- for (auto &chunk : sig.__chunks) {
+ for (auto &chunk : sig.chunks()) {
assert(chunk.width == 1);
- if (dont_care.extract(chunk).__width > 0)
+ if (dont_care.extract(chunk).size() > 0)
chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
}
sig.optimize();
ce.values_map.apply(sig);
sig.expand();
- for (auto &chunk : sig.__chunks) {
+ for (auto &chunk : sig.chunks()) {
assert(chunk.width == 1);
if (chunk.wire != NULL)
chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
}
sig.optimize();
- if (sig.__width == 0)
+ if (sig.size() == 0)
return RTLIL::Const();
- assert(sig.__chunks.size() == 1 && sig.__chunks[0].wire == NULL);
- return sig.__chunks[0].data;
+ assert(sig.chunks().size() == 1 && sig.chunks()[0].wire == NULL);
+ return sig.chunks()[0].data;
}
static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map<RTLIL::Const, int> &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care)
return;
}
- log_assert(undef.__width > 0);
+ log_assert(undef.size() > 0);
log_assert(ce.stop_signals.check_all(undef));
undef = undef.extract(0, 1);
// Initialize fsm data struct
FsmData fsm_data;
- fsm_data.num_inputs = ctrl_in.__width;
- fsm_data.num_outputs = ctrl_out.__width;
+ fsm_data.num_inputs = ctrl_in.size();
+ fsm_data.num_outputs = ctrl_out.size();
fsm_data.state_bits = wire->width;
fsm_data.reset_state = -1;
for (auto &it : states) {
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = new RTLIL::Wire;
unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
- unconn_wire->width = unconn_sig.__width;
+ unconn_wire->width = unconn_sig.size();
module->wires[unconn_wire->name] = unconn_wire;
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections[cellport.second]);
}
sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
}
if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections.count("\\Y") > 0 &&
- cell_it.second->connections["\\Y"].__width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
+ cell_it.second->connections["\\Y"].size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
or_sig.append(RTLIL::SigSpec(state_onehot, 1, in_state));
or_sig.optimize();
- if (or_sig.__width == 0)
+ if (or_sig.size() == 0)
continue;
RTLIL::SigSpec and_sig;
- if (eq_sig_a.__width > 0)
+ if (eq_sig_a.size() > 0)
{
RTLIL::Wire *eq_wire = new RTLIL::Wire;
eq_wire->name = NEW_ID;
eq_cell->connections["\\Y"] = RTLIL::SigSpec(eq_wire);
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.__width);
- eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.__width);
+ eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
+ eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->add(eq_cell);
and_sig.append(RTLIL::SigSpec(eq_wire));
}
- if (or_sig.__width < num_states-int(fullstate_cache.size()))
+ if (or_sig.size() < num_states-int(fullstate_cache.size()))
{
- if (or_sig.__width == 1)
+ if (or_sig.size() == 1)
{
and_sig.append(or_sig);
}
or_cell->connections["\\A"] = or_sig;
or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire);
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.__width);
+ or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->add(or_cell);
}
}
- switch (and_sig.__width)
+ switch (and_sig.size())
{
case 2:
{
}
}
- if (cases_vector.__width > 1) {
+ if (cases_vector.size() > 1) {
RTLIL::Cell *or_cell = new RTLIL::Cell;
or_cell->name = NEW_ID;
or_cell->type = "$reduce_or";
or_cell->connections["\\A"] = cases_vector;
or_cell->connections["\\Y"] = output;
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.__width);
+ or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->add(or_cell);
- } else if (cases_vector.__width == 1) {
+ } else if (cases_vector.size() == 1) {
module->connections.push_back(RTLIL::SigSig(output, cases_vector));
} else {
module->connections.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1)));
eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i);
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.__width);
- eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.__width);
+ eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
+ eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->add(eq_cell);
}
mux_cell->connections["\\B"] = sig_b;
mux_cell->connections["\\S"] = sig_s;
mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire);
- mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.__width);
- mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.__width);
+ mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
+ mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
module->add(mux_cell);
}
bool signal_is_unused(RTLIL::SigSpec sig)
{
- assert(sig.__width == 1);
+ assert(sig.size() == 1);
sig.optimize();
- RTLIL::Wire *wire = sig.__chunks[0].wire;
- int bit = sig.__chunks[0].offset;
+ RTLIL::Wire *wire = sig.chunks()[0].wire;
+ int bit = sig.chunks()[0].offset;
if (!wire || wire->attributes.count("\\unused_bits") == 0)
return false;
void opt_const_and_unused_inputs()
{
RTLIL::SigSpec ctrl_in = cell->connections["\\CTRL_IN"];
- std::vector<bool> ctrl_in_used(ctrl_in.__width);
+ std::vector<bool> ctrl_in_used(ctrl_in.size());
std::vector<FsmData::transition_t> new_transition_table;
for (auto &tr : fsm_data.transition_table) {
- for (int i = 0; i < ctrl_in.__width; i++) {
+ for (int i = 0; i < ctrl_in.size(); i++) {
RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1);
if (ctrl_bit.is_fully_const()) {
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit)
{
RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"];
- for (int i = 0; i < ctrl_in.__width; i++)
- for (int j = i+1; j < ctrl_in.__width; j++)
+ for (int i = 0; i < ctrl_in.size(); i++)
+ for (int j = i+1; j < ctrl_in.size(); j++)
if (ctrl_in.extract(i, 1) == ctrl_in.extract(j, 1))
{
log(" Optimize handling of signal %s that is connected to inputs %d and %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j);
RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"];
RTLIL::SigSpec &ctrl_out = cell->connections["\\CTRL_OUT"];
- for (int j = 0; j < ctrl_out.__width; j++)
- for (int i = 0; i < ctrl_in.__width; i++)
+ for (int j = 0; j < ctrl_out.size(); j++)
+ for (int i = 0; i < ctrl_in.size(); i++)
if (ctrl_in.extract(i, 1) == ctrl_out.extract(j, 1))
{
log(" Optimize handling of signal %s that is connected to input %d and output %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j);
log(" Input signals:\n");
RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"];
sig_in.expand();
- for (size_t i = 0; i < sig_in.__chunks.size(); i++)
- log(" %3zd: %s\n", i, log_signal(sig_in.__chunks[i]));
+ for (size_t i = 0; i < sig_in.chunks().size(); i++)
+ log(" %3zd: %s\n", i, log_signal(sig_in.chunks()[i]));
log("\n");
log(" Output signals:\n");
RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"];
sig_out.expand();
- for (size_t i = 0; i < sig_out.__chunks.size(); i++)
- log(" %3zd: %s\n", i, log_signal(sig_out.__chunks[i]));
+ for (size_t i = 0; i < sig_out.chunks().size(); i++)
+ log(" %3zd: %s\n", i, log_signal(sig_out.chunks()[i]));
log("\n");
log(" State encoding:\n");
for (auto &conn : i2.second->connections) {
if (conn.first[0] != '$')
portnames.insert(conn.first);
- portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.__width);
+ portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size());
}
for (auto ¶ : i2.second->parameters)
parameters.insert(para.first);
RTLIL::Module *mod = design->modules[cell->type];
for (auto &conn : cell->connections) {
- int conn_size = conn.second.__width;
+ int conn_size = conn.second.size();
std::string portname = conn.first;
if (portname.substr(0, 1) == "$") {
int port_id = atoi(portname.substr(1).c_str());
void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
{
- for (auto &c : sig.__chunks)
+ for (auto &c : sig.chunks())
if (c.wire != NULL)
flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
}
for (RTLIL::Cell *cell : submod.cells) {
RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
for (auto &conn : new_cell->connections)
- for (auto &c : conn.second.__chunks)
+ for (auto &c : conn.second.chunks())
if (c.wire != NULL) {
assert(wire_flags.count(c.wire) > 0);
c.wire = wire_flags[c.wire].new_wire;
sig_wr_clk_enable.optimize();
sig_wr_clk_polarity.optimize();
- assert(sig_wr_clk.__width == wr_ports);
- assert(sig_wr_clk_enable.__width == wr_ports && sig_wr_clk_enable.is_fully_const());
- assert(sig_wr_clk_polarity.__width == wr_ports && sig_wr_clk_polarity.is_fully_const());
- assert(sig_wr_addr.__width == wr_ports * addr_bits);
- assert(sig_wr_data.__width == wr_ports * memory->width);
- assert(sig_wr_en.__width == wr_ports * memory->width);
+ assert(sig_wr_clk.size() == wr_ports);
+ assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
+ assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
+ assert(sig_wr_addr.size() == wr_ports * addr_bits);
+ assert(sig_wr_data.size() == wr_ports * memory->width);
+ assert(sig_wr_en.size() == wr_ports * memory->width);
mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
- mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.__chunks[0].data : RTLIL::Const(0, 0);
- mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks()[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0);
mem->connections["\\WR_CLK"] = sig_wr_clk;
mem->connections["\\WR_ADDR"] = sig_wr_addr;
sig_rd_clk_polarity.optimize();
sig_rd_transparent.optimize();
- assert(sig_rd_clk.__width == rd_ports);
- assert(sig_rd_clk_enable.__width == rd_ports && sig_rd_clk_enable.is_fully_const());
- assert(sig_rd_clk_polarity.__width == rd_ports && sig_rd_clk_polarity.is_fully_const());
- assert(sig_rd_addr.__width == rd_ports * addr_bits);
- assert(sig_rd_data.__width == rd_ports * memory->width);
+ assert(sig_rd_clk.size() == rd_ports);
+ assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
+ assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
+ assert(sig_rd_addr.size() == rd_ports * addr_bits);
+ assert(sig_rd_data.size() == rd_ports * memory->width);
mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
- mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.__chunks[0].data : RTLIL::Const(0, 0);
- mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0);
- mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.__chunks[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks()[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks()[0].data : RTLIL::Const(0, 0);
mem->connections["\\RD_CLK"] = sig_rd_clk;
mem->connections["\\RD_ADDR"] = sig_rd_addr;
normalize_sig(module, sig);
sig.expand();
- for (size_t i = 0; i < sig.__chunks.size(); i++)
+ for (size_t i = 0; i < sig.chunks().size(); i++)
{
- RTLIL::SigChunk &chunk = sig.__chunks[i];
+ RTLIL::SigChunk &chunk = sig.chunks()[i];
if (chunk.wire == NULL)
continue;
normalize_sig(module, q_norm);
RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]);
- if (d.__width != 1)
+ if (d.size() != 1)
continue;
- assert(d.__chunks.size() == 1);
- chunk = d.__chunks[0];
+ assert(d.chunks().size() == 1);
+ chunk = d.chunks()[0];
clk = cell->connections["\\CLK"];
clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
goto replaced_this_bit;
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = sstr.str();
- wire->width = sig.__width;
+ wire->width = sig.size();
module->wires[wire->name] = wire;
RTLIL::SigSpec newsig(wire);
RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
RTLIL::SigSpec refclock;
RTLIL::State refclock_pol = RTLIL::State::Sx;
- for (int i = 0; i < clocks.__width; i++) {
+ for (int i = 0; i < clocks.size(); i++) {
RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width);
if (wr_en.is_fully_const() && !wr_en.as_bool()) {
static_ports.insert(i);
cell->name.c_str(), module->name.c_str(), i);
return;
}
- if (refclock.__width == 0) {
+ if (refclock.size() == 0) {
refclock = clocks.extract(i, 1);
refclock_pol = clocks_pol.bits[i];
}
c->connections["\\Y"] = w_seladdr;
int wr_offset = 0;
- while (wr_offset < wr_en.__width)
+ while (wr_offset < wr_en.size())
{
int wr_width = 1;
RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1);
- while (wr_offset + wr_width < wr_en.__width) {
+ while (wr_offset + wr_width < wr_en.size()) {
RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1);
if (next_wr_bit != wr_bit)
break;
created_conditions++;
}
- if (terms.__width > 1)
+ if (terms.size() > 1)
terms = module->ReduceAnd(NEW_ID, terms);
return conditions_logic_cache[conditions] = terms;
// this is the naive version of the function that does not care about grouping the EN bits.
RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits);
- RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.__width), inv_mask_bits, do_mask);
+ RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.size()), inv_mask_bits, do_mask);
RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits);
return result;
}
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::pair<int, std::vector<int>>> groups;
RTLIL::SigSpec grouped_bits, grouped_mask_bits;
- for (int i = 0; i < bits.__width; i++) {
+ for (int i = 0; i < bits.size(); i++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
if (groups.count(key) == 0) {
- groups[key].first = grouped_bits.__width;
+ groups[key].first = grouped_bits.size();
grouped_bits.append_bit(v_bits[i]);
grouped_mask_bits.append_bit(v_mask_bits[i]);
}
std::vector<RTLIL::SigBit> grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits);
RTLIL::SigSpec result;
- for (int i = 0; i < bits.__width; i++) {
+ for (int i = 0; i < bits.size(); i++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
result.append_bit(grouped_result.at(groups.at(key).first));
}
// Create the new merged_data signal.
- RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.__width);
+ RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.size());
RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data);
RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data));
static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool ®s, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires)
{
- assert(s1.__width == 1);
- assert(s2.__width == 1);
- assert(s1.__chunks.size() == 1);
- assert(s2.__chunks.size() == 1);
+ assert(s1.size() == 1);
+ assert(s2.size() == 1);
+ assert(s1.chunks().size() == 1);
+ assert(s2.chunks().size() == 1);
- RTLIL::Wire *w1 = s1.__chunks[0].wire;
- RTLIL::Wire *w2 = s2.__chunks[0].wire;
+ RTLIL::Wire *w1 = s1.chunks()[0].wire;
+ RTLIL::Wire *w2 = s2.chunks()[0].wire;
if (w1 == NULL || w2 == NULL)
return w2 == NULL;
} else {
s1.expand();
s2.expand();
- assert(s1.__chunks.size() == s2.__chunks.size());
+ assert(s1.chunks().size() == s2.chunks().size());
RTLIL::SigSig new_conn;
- for (size_t i = 0; i < s1.__chunks.size(); i++)
- if (s1.__chunks[i] != s2.__chunks[i]) {
- new_conn.first.append(s1.__chunks[i]);
- new_conn.second.append(s2.__chunks[i]);
+ for (size_t i = 0; i < s1.chunks().size(); i++)
+ if (s1.chunks()[i] != s2.chunks()[i]) {
+ new_conn.first.append(s1.chunks()[i]);
+ new_conn.second.append(s2.chunks()[i]);
}
- if (new_conn.first.__width > 0) {
+ if (new_conn.first.size() > 0) {
new_conn.first.optimize();
new_conn.second.optimize();
used_signals.add(new_conn.first);
if (!used_signals_nodrivers.check_any(sig)) {
std::string unused_bits;
sig.expand();
- for (size_t i = 0; i < sig.__chunks.size(); i++) {
- if (sig.__chunks[i].wire == NULL)
+ for (size_t i = 0; i < sig.chunks().size(); i++) {
+ if (sig.chunks()[i].wire == NULL)
continue;
if (!used_signals_nodrivers.check_any(sig)) {
if (!unused_bits.empty())
all_signals.del(driven_signals);
RTLIL::SigSpec undriven_signals = all_signals.export_all();
- for (auto &c : undriven_signals.__chunks)
+ for (auto &c : undriven_signals.chunks())
{
RTLIL::SigSpec sig = c;
if (c.wire->name[0] == '$')
sig = used_signals.extract(sig);
- if (sig.__width == 0)
+ if (sig.size() == 0)
continue;
log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
{
RTLIL::SigSpec Y = cell->connections[out_port];
- out_val.extend_u0(Y.__width, false);
+ out_val.extend_u0(Y.size(), false);
log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
cell->type.c_str(), cell->name.c_str(), info.c_str(),
RTLIL::SigSpec sig_y = sigmap(cell->connections.at("\\Y"));
if (extend_u0) {
- sig_a.extend_u0(sig_y.__width, a_signed);
- sig_b.extend_u0(sig_y.__width, b_signed);
+ sig_a.extend_u0(sig_y.size(), a_signed);
+ sig_b.extend_u0(sig_y.size(), b_signed);
} else {
- sig_a.extend(sig_y.__width, a_signed);
- sig_b.extend(sig_y.__width, b_signed);
+ sig_a.extend(sig_y.size(), a_signed);
+ sig_b.extend(sig_y.size(), b_signed);
}
std::vector<RTLIL::SigBit> bits_a = sig_a, bits_b = sig_b, bits_y = sig_y;
for (auto &it : grouped_bits[i]) {
for (auto &bit : it.second) {
new_conn.first.append_bit(bit);
- new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.__width));
+ new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size()));
}
new_a.append_bit(it.first.first);
new_b.append_bit(it.first.second);
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
c->connections["\\A"] = new_a;
- c->parameters["\\A_WIDTH"] = new_a.__width;
+ c->parameters["\\A_WIDTH"] = new_a.size();
c->parameters["\\A_SIGNED"] = false;
if (b_name == "\\B") {
c->connections["\\B"] = new_b;
- c->parameters["\\B_WIDTH"] = new_b.__width;
+ c->parameters["\\B_WIDTH"] = new_b.size();
c->parameters["\\B_SIGNED"] = false;
}
for (auto &cell_it : module->cells)
if (design->selected(module, cell_it.second)) {
if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") &&
- cell_it.second->connections["\\A"].__width == 1 && cell_it.second->connections["\\Y"].__width == 1)
+ cell_it.second->connections["\\A"].size() == 1 && cell_it.second->connections["\\Y"].size() == 1)
invert_map[assign_map(cell_it.second->connections["\\Y"])] = assign_map(cell_it.second->connections["\\A"]);
cells.push_back(cell_it.second);
}
cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
else
- replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").__width));
+ replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").size()));
goto next_cell;
}
}
- if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].__width == 1 &&
+ if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].size() == 1 &&
invert_map.count(assign_map(cell->connections["\\A"])) != 0) {
replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"])));
goto next_cell;
RTLIL::SigSpec new_a, new_b;
a.expand(), b.expand();
- assert(a.__chunks.size() == b.__chunks.size());
- for (size_t i = 0; i < a.__chunks.size(); i++) {
- if (a.__chunks[i].wire == NULL && b.__chunks[i].wire == NULL && a.__chunks[i].data.bits[0] != b.__chunks[i].data.bits[0] &&
- a.__chunks[i].data.bits[0] <= RTLIL::State::S1 && b.__chunks[i].data.bits[0] <= RTLIL::State::S1) {
+ assert(a.chunks().size() == b.chunks().size());
+ for (size_t i = 0; i < a.chunks().size(); i++) {
+ if (a.chunks()[i].wire == NULL && b.chunks()[i].wire == NULL && a.chunks()[i].data.bits[0] != b.chunks()[i].data.bits[0] &&
+ a.chunks()[i].data.bits[0] <= RTLIL::State::S1 && b.chunks()[i].data.bits[0] <= RTLIL::State::S1) {
RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1);
new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
replace_cell(module, cell, "empty", "\\Y", new_y);
goto next_cell;
}
- if (a.__chunks[i] == b.__chunks[i])
+ if (a.chunks()[i] == b.chunks()[i])
continue;
- new_a.append(a.__chunks[i]);
- new_b.append(b.__chunks[i]);
+ new_a.append(a.chunks()[i]);
+ new_b.append(b.chunks()[i]);
}
- if (new_a.__width == 0) {
+ if (new_a.size() == 0) {
RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0);
new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
replace_cell(module, cell, "empty", "\\Y", new_y);
goto next_cell;
}
- if (new_a.__width < a.__width || new_b.__width < b.__width) {
+ if (new_a.size() < a.size() || new_b.size() < b.size()) {
new_a.optimize();
new_b.optimize();
cell->connections["\\A"] = new_a;
cell->connections["\\B"] = new_b;
- cell->parameters["\\A_WIDTH"] = new_a.__width;
- cell->parameters["\\B_WIDTH"] = new_b.__width;
+ cell->parameters["\\A_WIDTH"] = new_a.size();
+ cell->parameters["\\B_WIDTH"] = new_b.size();
}
}
RTLIL::SigSpec a = assign_map(cell->connections["\\A"]);
RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
- if (a.is_fully_const() && a.__width <= 32 && a.as_int() == 1)
+ if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1)
identity_wrt_b = true;
- if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1)
+ if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
identity_wrt_a = true;
}
{
RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
- if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1)
+ if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
identity_wrt_a = true;
}
if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
RTLIL::SigSpec new_a, new_b, new_s;
- int width = cell->connections.at("\\A").__width;
+ int width = cell->connections.at("\\A").size();
if ((cell->connections.at("\\A").is_fully_undef() && cell->connections.at("\\B").is_fully_undef()) ||
cell->connections.at("\\S").is_fully_undef()) {
replace_cell(module, cell, "mux undef", "\\Y", cell->connections.at("\\A"));
goto next_cell;
}
- for (int i = 0; i < cell->connections.at("\\S").__width; i++) {
+ for (int i = 0; i < cell->connections.at("\\S").size(); i++) {
RTLIL::SigSpec old_b = cell->connections.at("\\B").extract(i*width, width);
RTLIL::SigSpec old_s = cell->connections.at("\\S").extract(i, 1);
if (old_b.is_fully_undef() || old_s.is_fully_undef())
new_s.append(old_s);
}
new_a = cell->connections.at("\\A");
- if (new_a.is_fully_undef() && new_s.__width > 0) {
- new_a = new_b.extract((new_s.__width-1)*width, width);
- new_b = new_b.extract(0, (new_s.__width-1)*width);
- new_s = new_s.extract(0, new_s.__width-1);
+ if (new_a.is_fully_undef() && new_s.size() > 0) {
+ new_a = new_b.extract((new_s.size()-1)*width, width);
+ new_b = new_b.extract(0, (new_s.size()-1)*width);
+ new_s = new_s.extract(0, new_s.size()-1);
}
- if (new_s.__width == 0) {
+ if (new_s.size() == 0) {
replace_cell(module, cell, "mux undef", "\\Y", new_a);
goto next_cell;
}
replace_cell(module, cell, "mux undef", "\\Y", new_s);
goto next_cell;
}
- if (cell->connections.at("\\S").__width != new_s.__width) {
+ if (cell->connections.at("\\S").size() != new_s.size()) {
cell->connections.at("\\A") = new_a;
cell->connections.at("\\B") = new_b;
cell->connections.at("\\S") = new_s;
- if (new_s.__width > 1) {
+ if (new_s.size() > 1) {
cell->type = "$pmux";
- cell->parameters["\\S_WIDTH"] = new_s.__width;
+ cell->parameters["\\S_WIDTH"] = new_s.size();
} else {
cell->type = "$mux";
cell->parameters.erase("\\S_WIDTH");
assign_map.apply(a); \
if (a.is_fully_const()) { \
a.optimize(); \
- if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \
+ if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
- RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, dummy_arg, \
+ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, dummy_arg, \
cell->parameters["\\A_SIGNED"].as_bool(), false, \
cell->parameters["\\Y_WIDTH"].as_int())); \
replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \
assign_map.apply(a), assign_map.apply(b); \
if (a.is_fully_const() && b.is_fully_const()) { \
a.optimize(), b.optimize(); \
- if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \
- if (b.__chunks.empty()) b.__chunks.push_back(RTLIL::SigChunk()); \
- RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, b.__chunks[0].data, \
+ if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
+ if (b.chunks().empty()) b.chunks().push_back(RTLIL::SigChunk()); \
+ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, b.chunks()[0].data, \
cell->parameters["\\A_SIGNED"].as_bool(), \
cell->parameters["\\B_SIGNED"].as_bool(), \
cell->parameters["\\Y_WIDTH"].as_int())); \
RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]);
- if (sig_b.is_fully_const() && sig_b.__width <= 32)
+ if (sig_b.is_fully_const() && sig_b.size() <= 32)
std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true;
- if (sig_a.is_fully_def() && sig_a.__width <= 32)
+ if (sig_a.is_fully_def() && sig_a.size() <= 32)
{
int a_val = sig_a.as_int();
log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
cell->name.c_str(), module->name.c_str());
- module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width)));
+ module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
module->remove(cell);
OPT_DID_SOMETHING = true;
goto next_cell;
}
- for (int i = 1; i < (a_signed ? sig_a.__width-1 : sig_a.__width); i++)
+ for (int i = 1; i < (a_signed ? sig_a.size()-1 : sig_a.size()); i++)
if (a_val == (1 << i))
{
log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
muxinfo_t muxinfo;
muxinfo.cell = cell;
- for (int i = 0; i < sig_s.__width; i++) {
- RTLIL::SigSpec sig = sig_b.extract(i*sig_a.__width, sig_a.__width);
+ for (int i = 0; i < sig_s.size(); i++) {
+ RTLIL::SigSpec sig = sig_b.extract(i*sig_a.size(), sig_a.size());
RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1));
portinfo_t portinfo;
for (int idx : sig2bits(sig)) {
if (live_ports.size() == 1)
{
- RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.__width, sig_a.__width);
+ RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size());
module->connections.push_back(RTLIL::SigSig(sig_y, sig_in));
module->cells.erase(mi.cell->name);
delete mi.cell;
RTLIL::SigSpec new_sig_a, new_sig_b, new_sig_s;
for (size_t i = 0; i < live_ports.size(); i++) {
- RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.__width, sig_a.__width);
+ RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.size(), sig_a.size());
if (i == live_ports.size()-1) {
new_sig_a = sig_in;
} else {
mi.cell->connections["\\A"] = new_sig_a;
mi.cell->connections["\\B"] = new_sig_b;
mi.cell->connections["\\S"] = new_sig_s;
- if (new_sig_s.__width == 1) {
+ if (new_sig_s.size() == 1) {
mi.cell->type = "$mux";
mi.cell->parameters.erase("\\S_WIDTH");
} else {
- mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width);
+ mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
}
}
}
std::vector<int> results;
assign_map.apply(sig);
sig.expand();
- for (auto &c : sig.__chunks)
+ for (auto &c : sig.chunks())
if (c.wire != NULL) {
bitDef_t bit(c.wire, c.offset);
if (bit2num.count(bit) == 0) {
sig_a.expand();
RTLIL::SigSpec new_sig_a;
- for (auto &chunk : sig_a.__chunks)
+ for (auto &chunk : sig_a.chunks())
{
if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) {
if (cell->type == "$reduce_and") {
}
new_sig_a.sort_and_unify();
- if (new_sig_a != sig_a || sig_a.__width != cell->connections["\\A"].__width) {
+ if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;
OPT_DID_SOMETHING = true;
}
cell->connections["\\A"] = new_sig_a;
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.__width);
+ cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
return;
}
std::set<RTLIL::SigSpec> handled_sig;
handled_sig.insert(sig_a);
- for (int i = 0; i < sig_s.__width; i++)
+ for (int i = 0; i < sig_s.size(); i++)
{
- RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.__width, sig_a.__width);
+ RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.size(), sig_a.size());
if (handled_sig.count(this_b) > 0)
continue;
RTLIL::SigSpec this_s = sig_s.extract(i, 1);
- for (int j = i+1; j < sig_s.__width; j++) {
- RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.__width, sig_a.__width);
+ for (int j = i+1; j < sig_s.size(); j++) {
+ RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.size(), sig_a.size());
if (this_b == that_b)
this_s.append(sig_s.extract(j, 1));
}
- if (this_s.__width > 1)
+ if (this_s.size() > 1)
{
RTLIL::Wire *reduce_or_wire = new RTLIL::Wire;
reduce_or_wire->name = NEW_ID;
reduce_or_cell->type = "$reduce_or";
reduce_or_cell->connections["\\A"] = this_s;
reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.__width);
+ reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->cells[reduce_or_cell->name] = reduce_or_cell;
handled_sig.insert(this_b);
}
- if (new_sig_s.__width != sig_s.__width) {
+ if (new_sig_s.size() != sig_s.size()) {
log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
did_something = true;
OPT_DID_SOMETHING = true;
total_count++;
}
- if (new_sig_s.__width == 0)
+ if (new_sig_s.size() == 0)
{
module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"]));
assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]);
{
cell->connections["\\B"] = new_sig_b;
cell->connections["\\S"] = new_sig_s;
- if (new_sig_s.__width > 1) {
- cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width);
+ if (new_sig_s.size() > 1) {
+ cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
} else {
cell->type = "$mux";
cell->parameters.erase("\\S_WIDTH");
cell->connections["\\A"].append(in_tuple.at(0));
cell->connections["\\B"] = RTLIL::SigSpec();
- for (int i = 1; i <= cell->connections["\\S"].__width; i++)
+ for (int i = 1; i <= cell->connections["\\S"].size(); i++)
for (auto &in_tuple : consolidated_in_tuples)
cell->connections["\\B"].append(in_tuple.at(i));
}
}
- if (sig_c.is_fully_const() && (!sig_r.__width || !has_init)) {
+ if (sig_c.is_fully_const() && (!sig_r.size() || !has_init)) {
if (val_rv.bits.size() == 0)
val_rv = val_init;
RTLIL::SigSig conn(sig_q, val_rv);
goto delete_dff;
}
- if (sig_d.is_fully_undef() && sig_r.__width && !has_init) {
+ if (sig_d.is_fully_undef() && sig_r.size() && !has_init) {
RTLIL::SigSig conn(sig_q, val_rv);
mod->connections.push_back(conn);
goto delete_dff;
}
- if (sig_d.is_fully_undef() && !sig_r.__width && has_init) {
+ if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
RTLIL::SigSig conn(sig_q, val_init);
mod->connections.push_back(conn);
goto delete_dff;
}
- if (sig_d.is_fully_const() && !sig_r.__width && !has_init) {
+ if (sig_d.is_fully_const() && !sig_r.size() && !has_init) {
RTLIL::SigSig conn(sig_q, sig_d);
mod->connections.push_back(conn);
goto delete_dff;
}
- if (sig_d == sig_q && !(sig_r.__width && has_init)) {
- if (sig_r.__width) {
+ if (sig_d == sig_q && !(sig_r.size() && has_init)) {
+ if (sig_r.size()) {
RTLIL::SigSig conn(sig_q, val_rv);
mod->connections.push_back(conn);
}
std::vector<std::string> dff_list;
for (auto &it : mod_it.second->cells) {
if (it.second->type == "$mux" || it.second->type == "$pmux") {
- if (it.second->connections.at("\\A").__width == it.second->connections.at("\\B").__width)
+ if (it.second->connections.at("\\A").size() == it.second->connections.at("\\B").size())
mux_drivers.insert(assign_map(it.second->connections.at("\\Y")), it.second);
continue;
}
RTLIL::SigSpec sig = it.second;
assign_map.apply(sig);
hash_string += "C " + it.first + "=";
- for (auto &chunk : sig.__chunks) {
+ for (auto &chunk : sig.chunks()) {
if (chunk.wire)
hash_string += "{" + chunk.wire->name + " " +
int_to_hash_string(chunk.offset) + " " +
static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity)
{
- if (signal.__width != 1)
+ if (signal.size() != 1)
return false;
if (signal == ref)
return true;
{
for (auto &action : cs->actions) {
if (unknown)
- rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.__width), &rval);
+ rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.size()), &rval);
else
rspec.replace(action.first, action.second, &rval);
}
for (auto sw : cs->switches) {
- if (sw->signal.__width == 0) {
+ if (sw->signal.size() == 0) {
for (auto cs2 : sw->cases)
apply_const(mod, rspec, rval, cs2, const_sig, polarity, unknown);
}
}
for (auto &action : sync->actions) {
RTLIL::SigSpec rspec = action.second;
- RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.__width);
+ RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size());
rspec.expand(), rval.expand();
- for (int i = 0; i < int(rspec.__chunks.size()); i++)
- if (rspec.__chunks[i].wire == NULL)
- rval.__chunks[i] = rspec.__chunks[i];
+ for (int i = 0; i < int(rspec.chunks().size()); i++)
+ if (rspec.chunks()[i].wire == NULL)
+ rval.chunks()[i] = rspec.chunks()[i];
rspec.optimize(), rval.optimize();
RTLIL::SigSpec last_rval;
for (int count = 0; rval != last_rval; count++) {
if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn)
for (auto &act : sync->actions) {
RTLIL::SigSpec arst_sig, arst_val;
- for (auto &chunk : act.first.__chunks)
+ for (auto &chunk : act.first.chunks())
if (chunk.wire && chunk.wire->attributes.count("\\init")) {
RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
value.extend(chunk.wire->width, false);
arst_sig.append(chunk);
arst_val.append(value.extract(chunk.offset, chunk.width));
}
- if (arst_sig.__width) {
+ if (arst_sig.size()) {
log("Added global reset to process %s: %s <- %s\n",
proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val));
arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val));
void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)
{
- if (sw->signal.__width > 0 && sw->signal.is_fully_const())
+ if (sw->signal.size() > 0 && sw->signal.is_fully_const())
{
int found_matching_case_idx = -1;
for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++)
sw->signal = RTLIL::SigSpec();
}
- if (sw->cases.size() == 1 && (sw->signal.__width == 0 || sw->cases[0]->compare.empty()))
+ if (sw->cases.size() == 1 && (sw->signal.size() == 0 || sw->cases[0]->compare.empty()))
{
did_something = true;
for (auto &action : sw->cases[0]->actions)
void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth)
{
for (size_t i = 0; i < cs->actions.size(); i++) {
- if (cs->actions[i].first.__width == 0) {
+ if (cs->actions[i].first.size() == 0) {
did_something = true;
cs->actions.erase(cs->actions.begin() + (i--));
}
bool did_something = true;
for (size_t i = 0; i < proc->syncs.size(); i++) {
for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++)
- if (proc->syncs[i]->actions[j].first.__width == 0)
+ if (proc->syncs[i]->actions[j].first.size() == 0)
proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--));
if (proc->syncs[i]->actions.size() == 0) {
delete proc->syncs[i];
for (auto sync : proc->syncs)
for (auto &action : sync->actions)
- if (action.first.__width > 0) {
+ if (action.first.size() > 0) {
lvalue = action.first;
lvalue.sort_and_unify();
break;
this_lvalue.append(action.first);
this_lvalue.sort_and_unify();
RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue);
- if (common_sig.__width > 0)
+ if (common_sig.size() > 0)
lvalue = common_sig;
}
static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
{
- RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.__width);
- RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.__width);
+ RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size());
+ RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size());
for (auto &it : async_rules)
{
else
log_abort();
- if (sync_low_signals.__width > 1) {
+ if (sync_low_signals.size() > 1) {
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$reduce_or";
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width);
+ cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = sync_low_signals;
cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID);
mod->add(cell);
}
- if (sync_low_signals.__width > 0) {
+ if (sync_low_signals.size() > 0) {
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$not";
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width);
+ cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = sync_low_signals;
cell->connections["\\Y"] = mod->addWire(NEW_ID);
mod->add(cell);
}
- if (sync_high_signals.__width > 1) {
+ if (sync_high_signals.size() > 1) {
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$reduce_or";
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.__width);
+ cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = sync_high_signals;
cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID);
inv_cell->name = NEW_ID;
inv_cell->type = "$not";
inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.__width);
- inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.__width);
+ inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
+ inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
inv_cell->connections["\\A"] = sync_value;
- inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.__width);
+ inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size());
mod->add(inv_cell);
RTLIL::Cell *mux_set_cell = new RTLIL::Cell;
mux_set_cell->name = NEW_ID;
mux_set_cell->type = "$mux";
- mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width);
+ mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
mux_set_cell->connections["\\A"] = sig_sr_set;
mux_set_cell->connections["\\B"] = sync_value;
mux_set_cell->connections["\\S"] = sync_high_signals;
- mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.__width);
+ mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size());
mod->add(mux_set_cell);
RTLIL::Cell *mux_clr_cell = new RTLIL::Cell;
mux_clr_cell->name = NEW_ID;
mux_clr_cell->type = "$mux";
- mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width);
+ mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
mux_clr_cell->connections["\\A"] = sig_sr_clr;
mux_clr_cell->connections["\\B"] = sync_value_inv;
mux_clr_cell->connections["\\S"] = sync_high_signals;
- mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.__width);
+ mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size());
mod->add(mux_clr_cell);
}
cell->name = sstr.str();
cell->type = "$dffsr";
cell->attributes = proc->attributes;
- cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width);
+ cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
std::stringstream sstr;
sstr << "$procdff$" << (RTLIL::autoidx++);
- RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.__width);
- RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.__width);
- RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.__width);
+ RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size());
+ RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
+ RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size());
RTLIL::Cell *inv_set = new RTLIL::Cell;
inv_set->name = NEW_ID;
inv_set->type = "$not";
inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.__width);
- inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.__width);
+ inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
+ inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
inv_set->connections["\\A"] = sig_set;
inv_set->connections["\\Y"] = sig_set_inv;
mod->add(inv_set);
RTLIL::Cell *mux_sr_set = new RTLIL::Cell;
mux_sr_set->name = NEW_ID;
mux_sr_set->type = "$mux";
- mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width);
- mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width);
+ mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
+ mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set;
mux_sr_set->connections["\\Y"] = sig_sr_set;
mux_sr_set->connections["\\S"] = set;
RTLIL::Cell *mux_sr_clr = new RTLIL::Cell;
mux_sr_clr->name = NEW_ID;
mux_sr_clr->type = "$mux";
- mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width);
- mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width);
+ mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
+ mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv;
mux_sr_clr->connections["\\Y"] = sig_sr_clr;
mux_sr_clr->connections["\\S"] = set;
cell->name = sstr.str();
cell->type = "$dffsr";
cell->attributes = proc->attributes;
- cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width);
+ cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
cell->attributes = proc->attributes;
mod->cells[cell->name] = cell;
- cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width);
+ cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
if (arst) {
cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1);
cell->parameters["\\ARST_VALUE"] = val_rst;
RTLIL::SigSpec sig = find_any_lvalue(proc);
bool free_sync_level = false;
- if (sig.__width == 0)
+ if (sig.size() == 0)
break;
log("Creating register for signal `%s.%s' using process `%s.%s'.\n",
mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str());
- RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width);
- RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width);
+ RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
+ RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
RTLIL::SyncRule *sync_level = NULL;
RTLIL::SyncRule *sync_edge = NULL;
RTLIL::SyncRule *sync_always = NULL;
for (auto sync : proc->syncs)
for (auto &action : sync->actions)
{
- if (action.first.extract(sig).__width == 0)
+ if (action.first.extract(sig).size() == 0)
continue;
if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {
if (sync_level != NULL && sync_level != sync) {
// log_error("Multiple level sensitive events found for this signal!\n");
many_async_rules[rstval].insert(sync_level);
- rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width);
+ rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
}
- rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width);
+ rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
sig.replace(action.first, action.second, &rstval);
sync_level = sync;
}
inputs.append(it->signal);
compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0);
}
- assert(inputs.__width == compare.__width);
+ assert(inputs.size() == compare.size());
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$ne";
cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1);
cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.__width);
- cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.__width);
+ cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
+ cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = inputs;
cell->connections["\\B"] = compare;
}
else
{
- rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width);
+ rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
sync_level = NULL;
}
}
sig.optimize();
if (rstval == sig) {
- rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width);
+ rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
sync_level = NULL;
}
sync_edge->signal, sync_level->signal, proc);
}
else
- gen_dff(mod, insig, rstval.__chunks[0].data, sig,
+ gen_dff(mod, insig, rstval.chunks()[0].data, sig,
sync_edge->type == RTLIL::SyncType::STp,
sync_level && sync_level->type == RTLIL::SyncType::ST1,
sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc);
log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
int offset = 0;
- for (size_t i = 0; i < lhs.__chunks.size(); i++) {
- if (lhs.__chunks[i].wire == NULL)
+ for (size_t i = 0; i < lhs.chunks().size(); i++) {
+ if (lhs.chunks()[i].wire == NULL)
continue;
- RTLIL::Wire *wire = lhs.__chunks[i].wire;
- RTLIL::SigSpec value = rhs.extract(offset, lhs.__chunks[i].width);
- if (value.__width != wire->width)
- log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.__chunks[i]), log_signal(value));
+ RTLIL::Wire *wire = lhs.chunks()[i].wire;
+ RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width);
+ if (value.size() != wire->width)
+ log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value));
log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value));
wire->attributes["\\init"] = value.as_const();
offset += wire->width;
static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs)
{
for (auto &action : cs->actions) {
- if (action.first.__width)
+ if (action.first.size())
return action.first;
}
for (auto sw : cs->switches)
for (auto cs2 : sw->cases) {
RTLIL::SigSpec sig = find_any_lvalue(cs2);
- if (sig.__width)
+ if (sig.size())
return sig;
}
{
for (auto &action : cs->actions) {
RTLIL::SigSpec lvalue = action.first.extract(sig);
- if (lvalue.__width)
+ if (lvalue.size())
sig = lvalue;
}
comp.expand();
// get rid of don't-care bits
- assert(sig.__width == comp.__width);
- for (int i = 0; i < comp.__width; i++)
- if (comp.__chunks[i].wire == NULL && comp.__chunks[i].data.bits[0] == RTLIL::State::Sa) {
+ assert(sig.size() == comp.size());
+ for (int i = 0; i < comp.size(); i++)
+ if (comp.chunks()[i].wire == NULL && comp.chunks()[i].data.bits[0] == RTLIL::State::Sa) {
sig.remove(i, 1);
comp.remove(i--, 1);
}
- if (comp.__width == 0)
+ if (comp.size() == 0)
return RTLIL::SigSpec();
sig.optimize();
comp.optimize();
- if (sig.__width == 1 && comp == RTLIL::SigSpec(1,1))
+ if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
{
mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig));
}
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0);
- eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.__width);
- eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.__width);
+ eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
+ eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
eq_cell->connections["\\A"] = sig;
static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw)
{
- assert(when_signal.__width == else_signal.__width);
+ assert(when_signal.size() == else_signal.size());
std::stringstream sstr;
sstr << "$procmux$" << (RTLIL::autoidx++);
// compare results
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
- if (ctrl_sig.__width == 0)
+ if (ctrl_sig.size() == 0)
return when_signal;
- assert(ctrl_sig.__width == 1);
+ assert(ctrl_sig.size() == 1);
// prepare multiplexer output signal
RTLIL::Wire *result_wire = new RTLIL::Wire;
result_wire->name = sstr.str() + "_Y";
- result_wire->width = when_signal.__width;
+ result_wire->width = when_signal.size();
mod->wires[result_wire->name] = result_wire;
// create the multiplexer itself
mux_cell->attributes = sw->attributes;
mod->cells[mux_cell->name] = mux_cell;
- mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.__width);
+ mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
mux_cell->connections["\\A"] = else_signal;
mux_cell->connections["\\B"] = when_signal;
mux_cell->connections["\\S"] = ctrl_sig;
static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
{
assert(last_mux_cell != NULL);
- assert(when_signal.__width == last_mux_cell->connections["\\A"].__width);
+ assert(when_signal.size() == last_mux_cell->connections["\\A"].size());
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
- assert(ctrl_sig.__width == 1);
+ assert(ctrl_sig.size() == 1);
last_mux_cell->type = "$pmux";
last_mux_cell->connections["\\S"].append(ctrl_sig);
last_mux_cell->connections["\\B"].append(when_signal);
- last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].__width;
+ last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].size();
}
static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
// detect groups of parallel cases
std::vector<int> pgroups(sw->cases.size());
if (!sw->get_bool_attribute("\\parallel_case")) {
- BitPatternPool pool(sw->signal.__width);
+ BitPatternPool pool(sw->signal.size());
bool extra_group_for_next_case = false;
for (size_t i = 0; i < sw->cases.size(); i++) {
RTLIL::CaseRule *cs2 = sw->cases[i];
if (cs2->compare.empty())
pgroups[i] = pgroups[i-1]+1;
if (pgroups[i] != pgroups[i-1])
- pool = BitPatternPool(sw->signal.__width);
+ pool = BitPatternPool(sw->signal.size());
}
for (auto pat : cs2->compare)
if (!pat.is_fully_const())
{
RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case);
- if (sig.__width == 0)
+ if (sig.size() == 0)
break;
if (first) {
log(" creating decoder for signal `%s'.\n", log_signal(sig));
- RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.__width));
+ RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size()));
mod->connections.push_back(RTLIL::SigSig(sig, value));
}
}
void run_checker(RTLIL::SigSpec &inputs)
{
- if (inputs.__width < mod1_inputs.__width) {
+ if (inputs.size() < mod1_inputs.size()) {
RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs;
inputs0.append(RTLIL::Const(0, 1));
inputs1.append(RTLIL::Const(1, 1));
if (ignore_x_mod1) {
sig1.expand(), sig2.expand();
- for (size_t i = 0; i < sig1.__chunks.size(); i++)
- if (sig1.__chunks.at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
- sig2.__chunks.at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
+ for (size_t i = 0; i < sig1.chunks().size(); i++)
+ if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
+ sig2.chunks().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
sig1.optimize(), sig2.optimize();
}
log_error("Failed to find solution to SAT problem.\n");
expected_y.expand();
- for (int i = 0; i < expected_y.__width; i++) {
+ for (int i = 0; i < expected_y.size(); i++) {
RTLIL::State solution_bit = y_values.at(i) ? RTLIL::State::S1 : RTLIL::State::S0;
- RTLIL::State expected_bit = expected_y.__chunks.at(i).data.bits.at(0);
+ RTLIL::State expected_bit = expected_y.chunks().at(i).data.bits.at(0);
if (model_undef) {
- if (y_values.at(expected_y.__width+i))
+ if (y_values.at(expected_y.size()+i))
solution_bit = RTLIL::State::Sx;
} else {
if (expected_bit == RTLIL::State::Sx)
}
if (solution_bit != expected_bit) {
std::string sat_bits, rtl_bits;
- for (int k = expected_y.__width-1; k >= 0; k--) {
- if (model_undef && y_values.at(expected_y.__width+k))
+ for (int k = expected_y.size()-1; k >= 0; k--) {
+ if (model_undef && y_values.at(expected_y.size()+k))
sat_bits += "x";
else
sat_bits += y_values.at(k) ? "1" : "0";
- rtl_bits += expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" :
- expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0";
+ rtl_bits += expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" :
+ expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0";
}
log_error("Found error in SAT model: y[%d] = %s, should be %s:\n SAT: %s\n RTL: %s\n %*s^\n",
int(i), log_signal(solution_bit), log_signal(expected_bit),
- sat_bits.c_str(), rtl_bits.c_str(), expected_y.__width-i-1, "");
+ sat_bits.c_str(), rtl_bits.c_str(), expected_y.size()-i-1, "");
}
}
std::vector<int> cmp_vars;
std::vector<bool> cmp_vals;
- std::vector<bool> y_undef(y_values.begin() + expected_y.__width, y_values.end());
+ std::vector<bool> y_undef(y_values.begin() + expected_y.size(), y_values.end());
- for (int i = 0; i < expected_y.__width; i++)
+ for (int i = 0; i < expected_y.size(); i++)
if (y_undef.at(i))
{
log(" Toggling undef bit %d to test undef gating.\n", i);
if (!ez.solve(y_vec, y_values, ez.IFF(y_vec.at(i), y_values.at(i) ? ez.FALSE : ez.TRUE)))
log_error("Failed to find solution with toggled bit!\n");
- cmp_vars.push_back(y_vec.at(expected_y.__width + i));
+ cmp_vars.push_back(y_vec.at(expected_y.size() + i));
cmp_vals.push_back(true);
}
else
cmp_vars.push_back(y_vec.at(i));
cmp_vals.push_back(y_values.at(i));
- cmp_vars.push_back(y_vec.at(expected_y.__width + i));
+ cmp_vars.push_back(y_vec.at(expected_y.size() + i));
cmp_vals.push_back(false);
}
while (!ce.eval(sig, undef)) {
// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
- ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width));
+ ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str());
rtl_sig.expand();
sat_check(module, recorded_set_vars, recorded_set_vals, sig, false);
sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
- } else if (rtl_sig.__width > 0) {
+ } else if (rtl_sig.size() > 0) {
sig.expand();
- if (rtl_sig.__width != sig.__width)
+ if (rtl_sig.size() != sig.size())
log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
- for (int i = 0; i < sig.__width; i++)
- if (rtl_sig.__chunks.at(i).data.bits.at(0) == RTLIL::State::Sx)
- sig.__chunks.at(i).data.bits.at(0) = RTLIL::State::Sx;
+ for (int i = 0; i < sig.size(); i++)
+ if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx)
+ sig.chunks().at(i).data.bits.at(0) = RTLIL::State::Sx;
}
log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());
}
if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const())
log_error("Failed to parse pattern %s!\n", pattern.c_str());
- if (sig.__width < total_input_width)
+ if (sig.size() < total_input_width)
log_error("Pattern %s is to short!\n", pattern.c_str());
patterns.push_back(sig.as_const());
if (invert_pattern) {
log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str());
if (!rhs.is_fully_const())
log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str());
- if (lhs.__width != rhs.__width)
+ if (lhs.size() != rhs.size())
log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
- it.first.c_str(), log_signal(lhs), lhs.__width, it.second.c_str(), log_signal(rhs), rhs.__width);
+ it.first.c_str(), log_signal(lhs), lhs.size(), it.second.c_str(), log_signal(rhs), rhs.size());
ce.set(lhs, rhs.as_const());
}
if (set_undef) {
while (!ce.eval(value, undef)) {
log("Failed to evaluate signal %s: Missing value for %s. -> setting to undef\n", log_signal(signal), log_signal(undef));
- ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width));
+ ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
undef = RTLIL::SigSpec();
}
log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value));
}
std::vector<std::string> tab_line;
- for (auto &c : tabsigs.__chunks)
+ for (auto &c : tabsigs.chunks())
tab_line.push_back(log_signal(c));
tab_sep_colidx = tab_line.size();
- for (auto &c : signal.__chunks)
+ for (auto &c : signal.chunks())
tab_line.push_back(log_signal(c));
tab.push_back(tab_line);
tab_line.clear();
- RTLIL::Const tabvals(0, tabsigs.__width);
+ RTLIL::Const tabvals(0, tabsigs.size());
do
{
ce.push();
log_signal(tabsigs), log_signal(tabvals), log_signal(this_undef));
return;
}
- ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.__width));
+ ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.size()));
undef.append(this_undef);
this_undef = RTLIL::SigSpec();
}
int pos = 0;
- for (auto &c : tabsigs.__chunks) {
+ for (auto &c : tabsigs.chunks()) {
tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width)));
pos += c.width;
}
pos = 0;
- for (auto &c : signal.__chunks) {
+ for (auto &c : signal.chunks()) {
tab_line.push_back(log_signal(value.extract(pos, c.width)));
pos += c.width;
}
}
log("\n");
- if (undef.__width > 0) {
+ if (undef.size() > 0) {
undef.sort_and_unify();
log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef));
}
{
RTLIL::Wire *w = new RTLIL::Wire;
w->name = cell->name + sep + RTLIL::unescape_id(it.first);
- w->width = it.second.__width;
+ w->width = it.second.size();
if (ct.cell_input(cell->type, it.first))
w->port_output = true;
if (ct.cell_output(cell->type, it.first))
if (grp[i].inverted)
{
- if (inv_sig.__width == 0)
+ if (inv_sig.size() == 0)
{
inv_sig = module->addWire(NEW_ID);
}
}
- if (all_conditions.__width != 1) {
+ if (all_conditions.size() != 1) {
RTLIL::Cell *reduce_cell = new RTLIL::Cell;
reduce_cell->name = NEW_ID;
reduce_cell->type = "$reduce_and";
- reduce_cell->parameters["\\A_WIDTH"] = all_conditions.__width;
+ reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
reduce_cell->parameters["\\Y_WIDTH"] = 1;
reduce_cell->parameters["\\A_SIGNED"] = 0;
reduce_cell->connections["\\A"] = all_conditions;
RTLIL::Cell *not_cell = new RTLIL::Cell;
not_cell->name = NEW_ID;
not_cell->type = "$not";
- not_cell->parameters["\\A_WIDTH"] = all_conditions.__width;
- not_cell->parameters["\\A_WIDTH"] = all_conditions.__width;
+ not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
+ not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
not_cell->parameters["\\A_SIGNED"] = 0;
not_cell->connections["\\A"] = all_conditions;
RTLIL::SigSpec lhs = sigmap(it.second);
RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
- log_assert(lhs.__width == rhs.__width);
+ log_assert(lhs.size() == rhs.size());
RTLIL::SigSpec removed_bits;
- for (int i = 0; i < lhs.__width; i++) {
+ for (int i = 0; i < lhs.size(); i++) {
RTLIL::SigSpec bit = lhs.extract(i, 1);
if (!satgen.initial_state.check_all(bit)) {
removed_bits.append(bit);
rhs.optimize();
removed_bits.optimize();
- if (removed_bits.__width)
+ if (removed_bits.size())
log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits));
- if (lhs.__width) {
+ if (lhs.size()) {
log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
big_lhs.append(lhs);
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
- if (lhs.__width != rhs.__width)
+ if (lhs.size() != rhs.size())
log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
- s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
+ s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
RTLIL::SigSpec rem = satgen.initial_state.export_all();
rem.remove(big_lhs);
big_lhs.append(rem);
- big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.__width));
+ big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.size()));
}
if (set_init_zero) {
RTLIL::SigSpec rem = satgen.initial_state.export_all();
rem.remove(big_lhs);
big_lhs.append(rem);
- big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.__width));
+ big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.size()));
}
- if (big_lhs.__width == 0) {
+ if (big_lhs.size() == 0) {
log("No constraints for initial state found.\n\n");
return;
}
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
- if (lhs.__width != rhs.__width)
+ if (lhs.size() != rhs.size())
log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
- s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
+ s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
- if (lhs.__width != rhs.__width)
+ if (lhs.size() != rhs.size())
log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
- s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
+ s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
log("Import set-constraint for this timestep: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
- if (lhs.__width != rhs.__width)
+ if (lhs.size() != rhs.size())
log_cmd_error("Proof expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
- s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
+ s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
log("Import proof-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
- if (lhs.__width != rhs.__width)
+ if (lhs.size() != rhs.size())
log_cmd_error("Proof-x expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
- s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
+ s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
log("Import proof-x-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
satgen.getAsserts(asserts_a, asserts_en, timestep);
asserts_a.expand();
asserts_en.expand();
- for (size_t i = 0; i < asserts_a.__chunks.size(); i++)
- log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.__chunks[i]), log_signal(asserts_en.__chunks[i]));
+ for (size_t i = 0; i < asserts_a.chunks().size(); i++)
+ log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.chunks()[i]), log_signal(asserts_en.chunks()[i]));
prove_bits.push_back(satgen.importAsserts(timestep));
}
std::vector<int> modelUndefExpressions;
- for (auto &c : modelSig.__chunks)
+ for (auto &c : modelSig.chunks())
if (c.wire != NULL)
{
ModelBlockInfo info;
RTLIL::SigSpec chunksig = c;
- info.width = chunksig.__width;
+ info.width = chunksig.size();
info.description = log_signal(chunksig);
for (int timestep = -1; timestep <= max_timestep; timestep++)
// Add initial state signals as collected by satgen
//
modelSig = satgen.initial_state.export_all();
- for (auto &c : modelSig.__chunks)
+ for (auto &c : modelSig.chunks())
if (c.wire != NULL)
{
ModelBlockInfo info;
info.timestep = 0;
info.offset = modelExpressions.size();
- info.width = chunksig.__width;
+ info.width = chunksig.size();
info.description = log_signal(chunksig);
modelInfo.insert(info);
RTLIL::SigSpec a2 = c2->connections.at("\\A");
RTLIL::SigSpec y2 = c2->connections.at("\\Y");
- int a_width = std::max(a1.__width, a2.__width);
- int y_width = std::max(y1.__width, y2.__width);
+ int a_width = std::max(a1.size(), a2.size());
+ int y_width = std::max(y1.size(), y2.size());
- if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
- if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+ if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+ if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
supercell->connections["\\Y"] = y;
module->add(supercell);
- RTLIL::SigSpec new_y1(y, y1.__width);
- RTLIL::SigSpec new_y2(y, y2.__width);
+ RTLIL::SigSpec new_y1(y, y1.size());
+ RTLIL::SigSpec new_y2(y, y2.size());
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));
RTLIL::SigSpec b2 = c2->connections.at("\\B");
RTLIL::SigSpec y2 = c2->connections.at("\\Y");
- int a_width = std::max(a1.__width, a2.__width);
- int b_width = std::max(b1.__width, b2.__width);
- int y_width = std::max(y1.__width, y2.__width);
+ int a_width = std::max(a1.size(), a2.size());
+ int b_width = std::max(b1.size(), b2.size());
+ int y_width = std::max(y1.size(), y2.size());
if (c1->type == "$shr" && a_signed)
{
a_width = std::max(y_width, a_width);
- if (a1.__width < y1.__width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.__width), true)->connections.at("\\Y");
- if (a2.__width < y2.__width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.__width), true)->connections.at("\\Y");
+ if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->connections.at("\\Y");
+ if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->connections.at("\\Y");
- if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
- if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
+ if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
+ if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
}
else
{
- if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
- if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+ if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+ if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
}
- if (b1.__width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
- if (b2.__width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
+ if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
+ if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act);
supercell->connections["\\Y"] = y;
supercell->check();
- RTLIL::SigSpec new_y1(y, y1.__width);
- RTLIL::SigSpec new_y2(y, y2.__width);
+ RTLIL::SigSpec new_y1(y, y1.size());
+ RTLIL::SigSpec new_y2(y, y2.size());
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));
if (activation_patterns_cache[cell].empty()) {
log("%sFound cell that is never activated: %s\n", indent, log_id(cell));
RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell];
- module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.__width)));
+ module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size())));
cells_to_remove.insert(cell);
}
int other_cell_select_score = 0;
for (auto &p : filtered_cell_activation_patterns)
- cell_select_score += p.first.__width;
+ cell_select_score += p.first.size();
for (auto &p : filtered_other_cell_activation_patterns)
- other_cell_select_score += p.first.__width;
+ other_cell_select_score += p.first.size();
RTLIL::Cell *supercell;
if (cell_select_score <= other_cell_select_score) {
needleSig.expand();
haystackSig.expand();
- for (int i = 0; i < std::min(needleSig.__width, haystackSig.__width); i++) {
- RTLIL::Wire *needleWire = needleSig.__chunks.at(i).wire, *haystackWire = haystackSig.__chunks.at(i).wire;
+ for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
+ RTLIL::Wire *needleWire = needleSig.chunks().at(i).wire, *haystackWire = haystackSig.chunks().at(i).wire;
if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))
return false;
RTLIL::SigSpec conn_sig = conn.second;
sigmap.apply(conn_sig);
conn_sig.expand();
- for (auto &chunk : conn_sig.__chunks)
+ for (auto &chunk : conn_sig.chunks())
if (chunk.wire != NULL)
sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)]++;
}
for (auto &conn : cell->connections)
{
- graph.createPort(cell->name, conn.first, conn.second.__width);
+ graph.createPort(cell->name, conn.first, conn.second.size());
if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
continue;
sigmap.apply(conn_sig);
conn_sig.expand();
- for (size_t i = 0; i < conn_sig.__chunks.size(); i++)
+ for (size_t i = 0; i < conn_sig.chunks().size(); i++)
{
- auto &chunk = conn_sig.__chunks[i];
+ auto &chunk = conn_sig.chunks()[i];
assert(chunk.width == 1);
if (chunk.wire == NULL) {
sigmap.apply(conn_sig);
conn_sig.expand();
- for (auto &chunk : conn_sig.__chunks)
+ for (auto &chunk : conn_sig.chunks())
if (sig_bit_ref.count(chunk) != 0) {
bit_ref_t &bit_ref = sig_bit_ref[chunk];
graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
sigmap.apply(conn_sig);
conn_sig.expand();
- for (auto &chunk : conn_sig.__chunks)
+ for (auto &chunk : conn_sig.chunks())
if (sig_bit_ref.count(chunk) != 0) {
bit_ref_t &bit_ref = sig_bit_ref[chunk];
graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
RTLIL::SigSpec sig = sigmap(conn.second);
if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
sig.expand();
- for (int i = 0; i < sig.__width; i++)
- for (auto &port : sig2port.find(sig.__chunks[i])) {
+ for (int i = 0; i < sig.size(); i++)
+ for (auto &port : sig2port.find(sig.chunks()[i])) {
RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1);
cell->connections.at(port.first).replace(port.second, bitsig);
}
for (auto cell : cells)
for (auto &conn : cell->connections) {
RTLIL::SigSpec sig = sigmap(conn.second);
- for (auto &chunk : sig.__chunks)
+ for (auto &chunk : sig.chunks())
if (chunk.wire != NULL)
wires.insert(chunk.wire);
}
newCell->parameters = cell->parameters;
for (auto &conn : cell->connections) {
RTLIL::SigSpec sig = sigmap(conn.second);
- for (auto &chunk : sig.__chunks)
+ for (auto &chunk : sig.chunks())
if (chunk.wire != NULL)
chunk.wire = newMod->wires.at(chunk.wire->name);
newCell->connections[conn.first] = sig;
void hilomap_worker(RTLIL::SigSpec &sig)
{
sig.expand();
- for (auto &c : sig.__chunks) {
+ for (auto &c : sig.chunks()) {
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi.width == 0) {
last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_INV_";
- gate->connections["\\A"] = sig_a.__chunks.at(i);
- gate->connections["\\Y"] = sig_y.__chunks.at(i);
+ gate->connections["\\A"] = sig_a.chunks().at(i);
+ gate->connections["\\Y"] = sig_y.chunks().at(i);
module->add(gate);
}
}
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_INV_";
- gate->connections["\\A"] = sig_t.__chunks.at(i);
- gate->connections["\\Y"] = sig_y.__chunks.at(i);
+ gate->connections["\\A"] = sig_t.chunks().at(i);
+ gate->connections["\\Y"] = sig_y.chunks().at(i);
module->add(gate);
}
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = gate_type;
- gate->connections["\\A"] = sig_a.__chunks.at(i);
- gate->connections["\\B"] = sig_b.__chunks.at(i);
- gate->connections["\\Y"] = sig_y.__chunks.at(i);
+ gate->connections["\\A"] = sig_a.chunks().at(i);
+ gate->connections["\\B"] = sig_b.chunks().at(i);
+ gate->connections["\\Y"] = sig_y.chunks().at(i);
module->add(gate);
}
}
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
- if (sig_y.__width == 0)
+ if (sig_y.size() == 0)
return;
- if (sig_a.__width == 0) {
- if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width)));
- if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width)));
- if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width)));
- if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width)));
- if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width)));
+ if (sig_a.size() == 0) {
+ if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+ if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+ if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+ if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+ if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
return;
}
- if (sig_y.__width > 1) {
- module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1)));
+ if (sig_y.size() > 1) {
+ module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
sig_y = sig_y.extract(0, 1);
}
RTLIL::SigSpec *last_output = NULL;
- while (sig_a.__width > 1)
+ while (sig_a.size() > 1)
{
- RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.__width / 2);
+ RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
sig_t.expand();
- for (int i = 0; i < sig_a.__width; i += 2)
+ for (int i = 0; i < sig_a.size(); i += 2)
{
- if (i+1 == sig_a.__width) {
- sig_t.append(sig_a.__chunks.at(i));
+ if (i+1 == sig_a.size()) {
+ sig_t.append(sig_a.chunks().at(i));
continue;
}
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = gate_type;
- gate->connections["\\A"] = sig_a.__chunks.at(i);
- gate->connections["\\B"] = sig_a.__chunks.at(i+1);
- gate->connections["\\Y"] = sig_t.__chunks.at(i/2);
+ gate->connections["\\A"] = sig_a.chunks().at(i);
+ gate->connections["\\B"] = sig_a.chunks().at(i+1);
+ gate->connections["\\Y"] = sig_t.chunks().at(i/2);
last_output = &gate->connections["\\Y"];
module->add(gate);
}
{
sig.expand();
- while (sig.__width > 1)
+ while (sig.size() > 1)
{
- RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.__width / 2);
+ RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
sig_t.expand();
- for (int i = 0; i < sig.__width; i += 2)
+ for (int i = 0; i < sig.size(); i += 2)
{
- if (i+1 == sig.__width) {
- sig_t.append(sig.__chunks.at(i));
+ if (i+1 == sig.size()) {
+ sig_t.append(sig.chunks().at(i));
continue;
}
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_OR_";
- gate->connections["\\A"] = sig.__chunks.at(i);
- gate->connections["\\B"] = sig.__chunks.at(i+1);
- gate->connections["\\Y"] = sig_t.__chunks.at(i/2);
+ gate->connections["\\A"] = sig.chunks().at(i);
+ gate->connections["\\B"] = sig.chunks().at(i+1);
+ gate->connections["\\Y"] = sig_t.chunks().at(i/2);
module->add(gate);
}
sig = sig_t;
}
- if (sig.__width == 0)
+ if (sig.size() == 0)
sig = RTLIL::SigSpec(0, 1);
}
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
- if (sig_y.__width == 0)
+ if (sig_y.size() == 0)
return;
- if (sig_y.__width > 1) {
- module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1)));
+ if (sig_y.size() > 1) {
+ module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
sig_y = sig_y.extract(0, 1);
}
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
- if (sig_y.__width == 0)
+ if (sig_y.size() == 0)
return;
- if (sig_y.__width > 1) {
- module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1)));
+ if (sig_y.size() > 1) {
+ module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
sig_y = sig_y.extract(0, 1);
}
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_MUX_";
- gate->connections["\\A"] = sig_a.__chunks.at(i);
- gate->connections["\\B"] = sig_b.__chunks.at(i);
+ gate->connections["\\A"] = sig_a.chunks().at(i);
+ gate->connections["\\B"] = sig_b.chunks().at(i);
gate->connections["\\S"] = cell->connections.at("\\S");
- gate->connections["\\Y"] = sig_y.__chunks.at(i);
+ gate->connections["\\Y"] = sig_y.chunks().at(i);
module->add(gate);
}
}
int offset = cell->parameters.at("\\OFFSET").as_int();
RTLIL::SigSpec sig_a = cell->connections.at("\\A");
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
- module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.__width)));
+ module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
}
static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = gate_type;
- gate->connections["\\S"] = sig_s.__chunks.at(i);
- gate->connections["\\R"] = sig_r.__chunks.at(i);
- gate->connections["\\Q"] = sig_q.__chunks.at(i);
+ gate->connections["\\S"] = sig_s.chunks().at(i);
+ gate->connections["\\R"] = sig_r.chunks().at(i);
+ gate->connections["\\Q"] = sig_q.chunks().at(i);
module->add(gate);
}
}
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\C"] = sig_clk;
- gate->connections["\\D"] = sig_d.__chunks.at(i);
- gate->connections["\\Q"] = sig_q.__chunks.at(i);
+ gate->connections["\\D"] = sig_d.chunks().at(i);
+ gate->connections["\\Q"] = sig_q.chunks().at(i);
module->add(gate);
}
}
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\C"] = sig_clk;
- gate->connections["\\S"] = sig_s.__chunks.at(i);
- gate->connections["\\R"] = sig_r.__chunks.at(i);
- gate->connections["\\D"] = sig_d.__chunks.at(i);
- gate->connections["\\Q"] = sig_q.__chunks.at(i);
+ gate->connections["\\S"] = sig_s.chunks().at(i);
+ gate->connections["\\R"] = sig_r.chunks().at(i);
+ gate->connections["\\D"] = sig_d.chunks().at(i);
+ gate->connections["\\Q"] = sig_q.chunks().at(i);
module->add(gate);
}
}
gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0;
gate->connections["\\C"] = sig_clk;
gate->connections["\\R"] = sig_rst;
- gate->connections["\\D"] = sig_d.__chunks.at(i);
- gate->connections["\\Q"] = sig_q.__chunks.at(i);
+ gate->connections["\\D"] = sig_d.chunks().at(i);
+ gate->connections["\\Q"] = sig_q.chunks().at(i);
module->add(gate);
}
}
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\E"] = sig_en;
- gate->connections["\\D"] = sig_d.__chunks.at(i);
- gate->connections["\\Q"] = sig_q.__chunks.at(i);
+ gate->connections["\\D"] = sig_d.chunks().at(i);
+ gate->connections["\\Q"] = sig_q.chunks().at(i);
module->add(gate);
}
}
static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
{
- for (size_t i = 0; i < sig.__chunks.size(); i++) {
- if (sig.__chunks[i].wire == NULL)
+ for (size_t i = 0; i < sig.chunks().size(); i++) {
+ if (sig.chunks()[i].wire == NULL)
continue;
- std::string wire_name = sig.__chunks[i].wire->name;
+ std::string wire_name = sig.chunks()[i].wire->name;
apply_prefix(prefix, wire_name);
assert(module->wires.count(wire_name) > 0);
- sig.__chunks[i].wire = module->wires[wire_name];
+ sig.chunks()[i].wire = module->wires[wire_name];
}
}
c.second = it.second;
apply_prefix(cell->name, c.first, module);
}
- if (c.second.__width > c.first.__width)
- c.second.remove(c.first.__width, c.second.__width - c.first.__width);
- if (c.second.__width < c.first.__width)
- c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.__width - c.second.__width));
- assert(c.first.__width == c.second.__width);
+ if (c.second.size() > c.first.size())
+ c.second.remove(c.first.size(), c.second.size() - c.first.size());
+ if (c.second.size() < c.first.size())
+ c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
+ assert(c.first.size() == c.second.size());
if (flatten_mode) {
// more conservative approach:
// connect internal and external wires
projects / yosys.git / commitdiff