*Programmer's Note:
As a Scalar Power ISA operation, like `lq` and `stq`, RS=RT+1.
To achieve the same big-integer rolling-accumulation effect
-as SVP64, instructions may be issued `madded r20,r4,r8,r20
-madded r21,r5,r9,r21` etc. where the first `madded` will have
+as SVP64: assuming the scalar to multiply is in r0,
+the vector to multiply by starts at r4 and the result vector
+in r20, instructions may be issued `madded r20,r4,r0,r20
+madded r21,r5,r0,r21` etc. where the first `madded` will have
stored the upper half of the 128-bit multiply into r21, such
that it may be picked up by the second `madded`. Repeat inline
to construct a larger bigint scalar-vector multiply,