sel-sched: correct reset of reset_sched_cycles_p (PR 85412)

2019-04-01  Andrey Belevantsev  <abel@ispras.ru>

	PR rtl-optimization/85412
	* sel-sched.c (sel_sched_region): Assign reset_sched_cycles_p before
	sel_sched_region_1, not after.

	* gcc.dg/pr85412.c: New test.

From-SVN: r270065

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9afd09bd7d9421f6fcb10e91eee0d3c9fed8ecae..7b745c611935bbc3446225dd195d424b6a1bd8e6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-04-01  Andrey Belevantsev  <abel@ispras.ru>
+
+       PR rtl-optimization/85412
+       * sel-sched.c (sel_sched_region): Assign reset_sched_cycles_p before
+       sel_sched_region_1, not after.
+
 2019-04-01  Andrey Belevantsev  <abel@ispras.ru>
 
        PR rtl-optimization/86928

diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c
index 338d7c097dfcf964aeb6963a6cf0e9f63a704121..552dd0b92636563ae841d635ed700c05e1513d43 100644 (file)
--- a/gcc/sel-sched.c
+++ b/gcc/sel-sched.c
@@ -7650,11 +7650,11 @@ sel_sched_region (int rgn)
       /* Schedule always selecting the next insn to make the correct data
         for bundling or other later passes.  */
       pipelining_p = false;
+      reset_sched_cycles_p = false;
       force_next_insn = 1;
       sel_sched_region_1 ();
       force_next_insn = 0;
     }
-  reset_sched_cycles_p = pipelining_p;
   sel_region_finish (reset_sched_cycles_p);
 }
 

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 244ae87b49510df9f47e5f6586e5ae386468f434..39e393487c477bad5c5ad710c5d8a47177839481 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2019-04-01  Andrey Belevantsev  <abel@ispras.ru>
+
+       PR rtl-optimization/85412
+       * gcc.dg/pr85412.c: New test.
+
 2019-04-01  Paolo Carlini  <paolo.carlini@oracle.com>
 
        PR c++/62207

diff --git a/gcc/testsuite/gcc.dg/pr85412.c b/gcc/testsuite/gcc.dg/pr85412.c
new file mode 100644 (file)
index 0000000..11b8cec
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr85412.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O1 -fpeephole2 -fschedule-insns2 -fsel-sched-pipelining -fselective-scheduling2 -ftree-loop-if-convert -fno-if-conversion -fno-move-loop-invariants -fno-split-wide-types -fno-tree-dominator-opts" } */
+/* { dg-additional-options "-march=bonnell" { target x86_64-*-* } } */
+
+__int128 jv;
+
+void
+zm (__int128 g9, unsigned short int sm, short int hk)
+{
+  while (hk < 1)
+    {
+      if (jv == 0)
+        sm *= g9;
+
+      if (sm < jv)
+        hk = sm;
+
+      g9 |= sm == hk;
+    }
+}