build/sim: allow defining start/end cycles for tracing

diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp
index 6821e20780e4424c339038a98641c36d1b5138c2..931b409952160ce963d4be1fdfa34ae6bac3d596 100644 (file)
--- a/litex/build/sim/core/veril.cpp
+++ b/litex/build/sim/core/veril.cpp
@@ -10,6 +10,8 @@
 #include <verilated.h>
 
 VerilatedVcdC* tfp;
+long tfp_start;
+long tfp_end;
 
 extern "C" void litex_sim_eval(void *vdut)
 {
@@ -22,9 +24,11 @@ extern "C" void litex_sim_init_cmdargs(int argc, char *argv[])
   Verilated::commandArgs(argc, argv);
 }
 
-extern "C" void litex_sim_init_tracer(void *vdut)
+extern "C" void litex_sim_init_tracer(void *vdut, long start, long end)
 {
   Vdut *dut = (Vdut*)vdut;
+  tfp_start = start;
+  tfp_end = end;
   Verilated::traceEverOn(true);
   tfp = new VerilatedVcdC;
   dut->trace(tfp, 99);
@@ -34,7 +38,15 @@ extern "C" void litex_sim_init_tracer(void *vdut)
 extern "C" void litex_sim_tracer_dump()
 {
   static unsigned int ticks=0;
-  tfp->dump(ticks++);
+  int dump = 1;
+  if (ticks < tfp_start)
+      dump = 0;
+  if (tfp_end != -1)
+      if (ticks > tfp_end)
+          dump = 0;
+  if (dump)
+      tfp->dump(ticks);
+  ticks++;
 }
 
 extern "C" int litex_sim_got_finish()

diff --git a/litex/build/sim/core/veril.h b/litex/build/sim/core/veril.h
index b8c5f16512631562b272a360f960d5561d2e8290..0bbc5ff9a72d1302ec6bc35fdf0104bdd4b41638 100644 (file)
--- a/litex/build/sim/core/veril.h
+++ b/litex/build/sim/core/veril.h
@@ -6,7 +6,7 @@
 #ifdef __cplusplus
 extern "C" void litex_sim_init_cmdargs(int argc, char *argv[]);
 extern "C" void litex_sim_eval(void *vdut);
-extern "C" void litex_sim_init_tracer(void *vdut);
+extern "C" void litex_sim_init_tracer(void *vdut, long start, long end)
 extern "C" void litex_sim_tracer_dump();
 extern "C" int litex_sim_got_finish();
 #if VM_COVERAGE

diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index e13cd3a9d19bc17687447f099b17f7dc4c6f2735..8d6a9a48f815c676ba48022c51c3d8eb559689cc 100644 (file)
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -60,7 +60,7 @@ def _generate_sim_cpp_struct(name, index, siglist):
     return content
 
 
-def _generate_sim_cpp(platform, trace=False):
+def _generate_sim_cpp(platform, trace=False, trace_start=0, trace_end=-1):
     content = """\
 #include <stdio.h>
 #include <stdlib.h>
@@ -69,7 +69,7 @@ def _generate_sim_cpp(platform, trace=False):
 #include <verilated.h>
 #include "dut_header.h"
 
-extern "C" void litex_sim_init_tracer(void *vdut);
+extern "C" void litex_sim_init_tracer(void *vdut, long start, long end);
 extern "C" void litex_sim_tracer_dump();
 
 extern "C" void litex_sim_dump()
@@ -80,17 +80,17 @@ extern "C" void litex_sim_dump()
     litex_sim_tracer_dump();
 """
     content  += """\
-}
+}}
 
 extern "C" void litex_sim_init(void **out)
-{
+{{
     Vdut *dut;
 
     dut = new Vdut;
 
-    litex_sim_init_tracer(dut);
+    litex_sim_init_tracer(dut, {},{});
 
-"""
+""".format(trace_start, trace_end)
     for args in platform.sim_requested:
         content += _generate_sim_cpp_struct(*args)
 
@@ -169,7 +169,8 @@ def _run_sim(build_name, as_root=False):
 class SimVerilatorToolchain:
     def build(self, platform, fragment, build_dir="build", build_name="dut",
             toolchain_path=None, serial="console", build=True, run=True, threads=1,
-            verbose=True, sim_config=None, trace=False, coverage=False):
+            verbose=True, sim_config=None, coverage=False,
+            trace=False, trace_start=0, trace_end=-1):
 
         # create build directory
         os.makedirs(build_dir, exist_ok=True)
@@ -191,7 +192,7 @@ class SimVerilatorToolchain:
 
             # generate cpp header/main/variables
             _generate_sim_h(platform)
-            _generate_sim_cpp(platform, trace)
+            _generate_sim_cpp(platform, trace, trace_start, trace_end)
             _generate_sim_variables(platform.verilog_include_paths)
 
             # generate sim config

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 033a0e45568efc3cd1d48afc2c5279bad531e9a1..01bab977abeba925c1c5eb36df65d9e3d6d315bb 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -200,6 +200,10 @@ def main():
                         help="enable Analyzer support")
     parser.add_argument("--trace", action="store_true",
                         help="enable VCD tracing")
+    parser.add_argument("--trace-start", default=0,
+                        help="cycle to start VCD tracing")
+    parser.add_argument("--trace-end", default=-1,
+                        help="cycle to end VCD tracing")
     args = parser.parse_args()
 
     soc_kwargs = soc_sdram_argdict(args)
@@ -237,10 +241,12 @@ def main():
         soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
     builder_kwargs["csr_csv"] = "csr.csv"
     builder = Builder(soc, **builder_kwargs)
-    vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, trace=args.trace)
+    vns = builder.build(run=False, threads=args.threads, sim_config=sim_config,
+        trace=args.trace, trace_start=int(args.trace_start), trace_end=int(args.trace_end))
     if args.with_analyzer:
         soc.analyzer.export_csv(vns, "analyzer.csv")
-    builder.build(build=False, threads=args.threads, sim_config=sim_config, trace=args.trace)
+    builder.build(build=False, threads=args.threads, sim_config=sim_config,
+        trace=args.trace, trace_start=int(args.trace_start), trace_end=int(args.trace_end))
 
 
 if __name__ == "__main__":