comments for why preinc is called for svstep

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 6919cd74337efdfcfe6e47f4f2086b4d70c0438b..ba681df3296458afe89443afdf41829e0178fb24 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1691,6 +1691,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         log("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
 
         # see if srcstep/dststep need skipping over masked-out predicate bits
+        # svstep also needs advancement because it calls SVSTATE_NEXT.
+        # bit the remaps get computed just after pre_inc moves them on
+        # with remap_set_steps substituting for PowerDecider2 not doing it,
+        # and SVSTATE_NEXT not being able to.use yield, the preinc on
+        # svstep is necessary for now.
         self.reset_remaps()
         if (self.is_svp64_mode or ins_name in ['svstep']):
             yield from self.svstate_pre_inc()