Other modern ISAs claiming to be Vectors are in fact Packed or Predicated SIMD.
True Cray-style Vector ISAs do not have Vertical-First or Data-Dependent
Fail-First because these are entirely novel Computer Science concepts
-(developnet of which entirely funded by NLnet, with gratitude).
+(development of which entirely funded by NLnet, with gratitude).
Bottom line there are zero comparable projects but the project has learned
significantly from past ISAs dating back as far as the early 1960s.
The key technical challenge in this project is to rework the special Simple-V
instructions (from the early iteration of four years ago) that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community.
-Based on the previous work of Vectorising RISC-V and POWER using Simple-V already, this project is well within the scope of the experienced teams at LibreSOC and RED Semiconductor, but is extremely detailed and comprehensive, requiring meticulous attention to detail and a very high standard of Project Management. This is a sustained standard and practices developed already over a five year period that will continue to be rigorously applied.
+Based on the previous work of Vectorising RISC-V and POWER using Simple-V already, this project is well within the scope of the experienced LibreSOC team, but is extremely detailed and comprehensive, requiring meticulous attention to detail and a very high standard of Project Management. This is a sustained standard and practices developed already over a five year period that will continue to be rigorously applied.
## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
projects / libreriscv.git / commitdiff