The EXTRACT_LAST_REDUCTION handling needs to generate a separate
comparison instruction that feeds the vector mask argument of the
IFN_EXTRACT_LAST call. We weren't checking whether that comparison
was supported, leading to an ICE on the testcase.
2019-12-29 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* tree-vect-stmts.c (vectorizable_condition): For extract-last
reductions, check that the target supports the required comparison
operation.
gcc/testsuite/
* gcc.dg/vect/vect-cond-12.c: New test.
From-SVN: r279752
+2019-12-29 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vect-stmts.c (vectorizable_condition): For extract-last
+ reductions, check that the target supports the required comparison
+ operation.
+
2019-12-27 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/iterators.md (V_INT_CONTAINER): Fix VNx2SF entry.
+2019-12-29 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gcc.dg/vect/vect-cond-12.c: New test.
+
2019-12-27 Richard Sandiford <richard.sandiford@arm.com>
* gcc.target/aarch64/sve/mixed_size_11.c: New test.
--- /dev/null
+/* { dg-do compile } */
+
+int
+f (int *x, short *y)
+{
+ int res = 100;
+ for (int i = 0; i < 40; ++i)
+ {
+ if (y[i] > 1)
+ res = x[i];
+ x[i] += y[i];
+ }
+ return res;
+}
cond_code = SSA_NAME;
}
+ if (TREE_CODE_CLASS (cond_code) == tcc_comparison
+ && reduction_type == EXTRACT_LAST_REDUCTION
+ && !expand_vec_cmp_expr_p (comp_vectype, vec_cmp_type, cond_code))
+ {
+ if (dump_enabled_p ())
+ dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
+ "reduction comparison operation not supported.\n");
+ return false;
+ }
+
if (!vec_stmt)
{
if (bitop1 != NOP_EXPR)