Tests for ld, lr, st, sr insns.
authorDavid Edelsohn <dje.gcc@gmail.com>
Mon, 10 Apr 1995 07:32:57 +0000 (07:32 +0000)
committerDavid Edelsohn <dje.gcc@gmail.com>
Mon, 10 Apr 1995 07:32:57 +0000 (07:32 +0000)
gas/testsuite/gas/arc/.Sanitize
gas/testsuite/gas/arc/ld.d [new file with mode: 0644]
gas/testsuite/gas/arc/ld.s [new file with mode: 0644]
gas/testsuite/gas/arc/st.d [new file with mode: 0644]
gas/testsuite/gas/arc/st.s [new file with mode: 0644]

index 881c373a951de2eddf058bf7afc0309ab182b6b5..a8d5b675b718d0481c59c32eada48d5770569da1 100644 (file)
@@ -35,12 +35,17 @@ insn3.s
 insn3.d
 j.s
 j.d
+ld.s
+ld.s
 math.s
 math.d
 mul64.s
 mul64.d
 sshift.s
 sshift.d
+st.s
+st.d
+
 Things-to-lose:
 
 Do-last:
diff --git a/gas/testsuite/gas/arc/ld.d b/gas/testsuite/gas/arc/ld.d
new file mode 100644 (file)
index 0000000..c3845a6
--- /dev/null
@@ -0,0 +1,30 @@
+#objdump: -dr
+#name: ld/lr
+
+# Test the ld/lr insn.
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+00000000 08008000      ld r0,\[r1\]
+00000004 00418800      ld r2,\[r3,r4\]
+00000008 08a30001      ld r5,\[r6,1\]
+0000000c 08e401ff      ld r7,\[r8,-1\]
+00000010 092500ff      ld r9,\[r10,255\]
+00000014 09660100      ld r11,\[r12,-256\]
+00000018 09a70100      ld r13,\[r14,-256\]
+0000001c 09e800ff      ld r15,\[r16,255\]
+00000020 023f3800      ld r17,\[305419896,sp\]
+00000028 0a7f0000      ld r19,\[0\]
+               RELOC: 0000002c R_ARC_32 foo
+00000030 0a9f0000      ld r20,\[4\]
+               RELOC: 00000034 R_ARC_32 foo
+00000038 081f8400      ldb r0,\[0\]
+0000003c 081f8800      ldw r0,\[0\]
+00000040 081f8200      ld.x r0,\[0\]
+00000044 081f9000      ld.a r0,\[0\]
+00000048 081fc000      ld.di r0,\[0\]
+0000004c 08005600      ldb.x.a.di r0,\[r0\]
+00000050 0800a000      lr r0,\[r1\]
+00000054 085fa000      lr r2,\[status\]
+00000058 087f2000      lr r3,\[305419896\]
diff --git a/gas/testsuite/gas/arc/ld.s b/gas/testsuite/gas/arc/ld.s
new file mode 100644 (file)
index 0000000..aa26719
--- /dev/null
@@ -0,0 +1,24 @@
+# ld/lr test
+       
+       ld      r0,[r1]
+       ld      r2,[r3,r4]
+       ld      r5,[r6,1]
+       ld      r7,[r8,-1]
+       ld      r9,[r10,255]
+       ld      r11,[r12,-256]
+       ld      r13,[r14,256]
+       ld      r15,[r16,-257]
+       ld      r17,[0x12345678,r28]
+       ld      r19,[foo]
+       ld      r20,[foo+4]
+
+       ldb     r0,[0]
+       ldw     r0,[0]
+       ld.x    r0,[0]
+       ld.a    r0,[0]
+       ld.di   r0,[0]
+       ldb.x.a.di r0,[r0]
+
+       lr      r0,[r1]
+       lr      r2,[status]
+       lr      r3,[0x12345678]
diff --git a/gas/testsuite/gas/arc/st.d b/gas/testsuite/gas/arc/st.d
new file mode 100644 (file)
index 0000000..9568712
--- /dev/null
@@ -0,0 +1,27 @@
+#objdump: -dr
+#name: st/sr
+
+# Test the st/sr insn.
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+00000000 10008000      st r0,\[r1\]
+00000004 10030a01      st r5,\[r6,1\]
+00000008 10040fff      st r7,\[r8,-1\]
+0000000c 100512ff      st r9,\[r10,255\]
+00000010 10061700      st r11,\[r12,-256\]
+00000014 10071b00      st r13,\[r14,-256\]
+00000018 10081eff      st r15,\[r16,255\]
+0000001c 101f2600      st r19,\[0\]
+               RELOC: 00000020 R_ARC_32 foo
+00000024 101f2800      st r20,\[4\]
+               RELOC: 00000028 R_ARC_32 foo
+0000002c 105f0000      stb r0,\[0\]
+00000034 109f0000      stw r0,\[0\]
+0000003c 111f0000      st.a r0,\[0\]
+00000044 141f0000      st.di r0,\[0\]
+0000004c 15400000      stb.a.di r0,\[r0\]
+00000050 12008000      sr r0,\[r1\]
+00000054 121f8400      sr r2,\[status\]
+00000058 121f0600      sr r3,\[305419896\]
diff --git a/gas/testsuite/gas/arc/st.s b/gas/testsuite/gas/arc/st.s
new file mode 100644 (file)
index 0000000..3e92914
--- /dev/null
@@ -0,0 +1,21 @@
+# st/sr test
+       
+       st      r0,[r1]
+       st      r5,[r6,1]
+       st      r7,[r8,-1]
+       st      r9,[r10,255]
+       st      r11,[r12,-256]
+       st      r13,[r14,256]
+       st      r15,[r16,-257]
+       st      r19,[foo]
+       st      r20,[foo+4]
+
+       stb     r0,[0]
+       stw     r0,[0]
+       st.a    r0,[0]
+       st.di   r0,[0]
+       stb.a.di r0,[r0]
+
+       sr      r0,[r1]
+       sr      r2,[status]
+       sr      r3,[0x12345678]