bus/wishbone/sram: accept memories < 32 bits

diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index d0c0c5b51cf1c952dc8e68647476fa02c0e6ac0e..b1d23233efbd6a4f2c14700ed0c46ce677c1f53d 100644 (file)
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -197,7 +197,7 @@ class Target(PureSimulable):
 class SRAM:
        def __init__(self, mem_or_size, bus=Interface()):
                if isinstance(mem_or_size, Memory):
-                       assert(mem_or_size.width == 32)
+                       assert(mem_or_size.width <= 32)
                        self.mem = mem_or_size
                else:
                        self.mem = Memory(32, mem_or_size//4)