arch-power: Refactor compare instructions

This changes the base class for integer compare instructions
and adds two new classes that are used to distinguish between
instructions using different operand types, i.e. register or
immediate, and comparison types, i.e. signed or unsigned. The
formats have also been updated to make use of the new base
classes.

Change-Id: Ic6feb803b3a22225d90b8712babd42889b67969d
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index 38c0dd0d39f617723d0438a6bfca5beaa76e77cc..75d4543e24c52c61e8959c3987f1c954da5b937e 100644 (file)
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -426,6 +426,62 @@ class IntDispArithOp : public IntArithOp
 };
 
 
+/**
+ * Class for integer compare operations.
+ */
+class IntCompOp : public IntOp
+{
+  protected:
+
+    uint32_t length;
+    uint32_t field;
+
+    /// Constructor
+    IntCompOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : IntOp(mnem, _machInst, __opClass),
+        length(machInst.l),
+        field(machInst.bf)
+    {
+    }
+};
+
+
+/**
+ * Class for integer immediate compare operations.
+ */
+class IntImmCompOp : public IntCompOp
+{
+  protected:
+
+    int32_t simm;
+
+    /// Constructor
+    IntImmCompOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : IntCompOp(mnem, _machInst, __opClass),
+        simm((int16_t)machInst.si)
+    {
+    }
+};
+
+
+/**
+ * Class for integer immediate compare logical operations.
+ */
+class IntImmCompLogicOp : public IntCompOp
+{
+  protected:
+
+    uint32_t uimm;
+
+    /// Constructor
+    IntImmCompLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : IntCompOp(mnem, _machInst, __opClass),
+        uimm(machInst.ui)
+    {
+    }
+};
+
+
 /**
  * Class for integer operations with a shift.
  */

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 06636a2f88b0239b273c2ab0598592ac14d376fe..d623506ff4966c3720988e08fcc39f4a4d0b6c7e 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -234,19 +234,18 @@ decode PO default Unknown::unknown() {
         }
     }
 
-    format IntImmOp {
-        10: cmpli({{
-            Xer xer = XER;
-            uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
-            CR = insertCRField(CR, BF, cr);
-            }});
+    format IntImmCompOp {
         11: cmpi({{
-            Xer xer = XER;
-            uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
-            CR = insertCRField(CR, BF, cr);
+            cr = makeCRField(Ra_sw, (int32_t)simm, xer.so);
             }});
     }
 
+    format IntImmCompLogicOp {
+        10: cmpli({{
+            cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
+            }});
+     }
+
     format IntImmLogicOp {
         24: ori({{ Ra = Rs | uimm; }});
         25: oris({{ Ra = Rs | (uimm << 16); }});
@@ -435,17 +434,13 @@ decode PO default Unknown::unknown() {
             }});
         }
 
-        format IntOp {
+        format IntCompOp {
             0: cmp({{
-                Xer xer = XER;
-                uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
-                CR = insertCRField(CR, BF, cr);
+                cr = makeCRField(Ra_sw, Rb_sw, xer.so);
             }});
 
             32: cmpl({{
-                Xer xer = XER;
-                uint32_t cr = makeCRField(Ra, Rb, xer.so);
-                CR = insertCRField(CR, BF, cr);
+                cr = makeCRField(Ra, Rb, xer.so);
             }});
         }
 

diff --git a/src/arch/power/isa/formats/integer.isa b/src/arch/power/isa/formats/integer.isa
index 6860c26a703f6d4c916bc468e6e779862eac3a27..9a3e0d8fde7f1e52c19111c2ca732b0294163a10 100644 (file)
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -217,6 +217,57 @@ def format IntDispArithOp(code, inst_flags = []) {{
 }};
 
 
+// Integer compare instructions.
+def format IntCompOp(code, inst_flags = []) {{
+
+    # Add code to setup variables
+    code = 'M5_VAR_USED uint32_t cr = 0;\n' + code
+    code += 'CR = insertCRField(CR, field, cr);\n'
+
+    # Add code to access XER
+    code = readXERCode + code
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenAluOp(name, Name, 'IntCompOp', code, inst_flags, BasicDecode,
+                 BasicConstructor)
+}};
+
+
+// Integer immediate compare instructions.
+def format IntImmCompOp(code, inst_flags = []) {{
+
+    # Add code to setup variables
+    code = 'M5_VAR_USED uint32_t cr = 0;\n' + code
+    code += 'CR = insertCRField(CR, field, cr);\n'
+
+    # Add code to access XER
+    code = readXERCode + code
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenAluOp(name, Name, 'IntImmCompOp', code, inst_flags, BasicDecode,
+                 BasicConstructor)
+}};
+
+
+// Integer immediate compare logical instructions.
+def format IntImmCompLogicOp(code, inst_flags = []) {{
+
+    # Add code to setup variables
+    code = 'M5_VAR_USED uint32_t cr = 0;\n' + code
+    code += 'CR = insertCRField(CR, field, cr);\n'
+
+    # Add code to access XER
+    code = readXERCode + code
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenAluOp(name, Name, 'IntImmCompLogicOp', code, inst_flags,
+                 BasicDecode, BasicConstructor)
+}};
+
+
 // Integer instructions that perform logic operations. The result is
 // always written into Ra. All instructions have 2 versions depending on
 // whether the Rc bit is set to compute the CR0 code. This is determined