MultiReg: remove idomain

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index dd3d3263046cc8c6cdf9b0294f3ddab80626fb41..fe76b2ec68842b360572568bf853f345cfea7b77 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -121,7 +121,7 @@ class XilinxMultiRegImpl(MultiRegImpl):
 class XilinxMultiReg:
        @staticmethod
        def lower(dr):
-               return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
+               return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
 
 class XilinxISEPlatform(GenericPlatform):
        def get_verilog(self, *args, special_overrides=dict(), **kwargs):