litescope: remove repeat mode on drivers (not useful) and cleanup

diff --git a/misoclib/tools/litescope/host/driver/etherbone.py b/misoclib/tools/litescope/host/driver/etherbone.py
index f7c5285a1f6f0684fefd25ec032dd05d1fc79126..66d4cfa2366d5a879d8f0fcb5fb0900ff5707468 100644 (file)
--- a/misoclib/tools/litescope/host/driver/etherbone.py
+++ b/misoclib/tools/litescope/host/driver/etherbone.py
@@ -23,12 +23,8 @@ class LiteScopeEtherboneDriver:
     def close(self):
         pass
 
-    def read(self, addr, burst_length=None, repeats=None):
-        def to_int(v):
-            return 1 if v is None else v
-        reads_addrs = []
-        for i in range(to_int(repeats)):
-            reads_addrs += [addr+4*j for j in range(to_int(burst_length))]
+    def read(self, addr, burst_length=1):
+        reads_addrs = [addr+4*j for j in range(burst_length)]
         reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
         record = EtherboneRecord()
         record.writes = None
@@ -54,8 +50,11 @@ class LiteScopeEtherboneDriver:
         datas = packet.records.pop().writes.get_datas()
         if self.debug:
             for i, data in enumerate(datas):
-                print("RD {:08X} @ {:08X}".format(data, addr + 4*(i%to_int(burst_length))))
-        return datas
+                print("RD {:08X} @ {:08X}".format(data, addr + 4*i))
+        if burst_length == 1:
+            return datas[0]
+        else:
+            return datas
 
     def write(self, addr, datas):
         if not isinstance(datas, list):

diff --git a/misoclib/tools/litescope/host/driver/pcie.py b/misoclib/tools/litescope/host/driver/pcie.py
index 97063aa02dce2b3f49bfc5e09c73f718af82c8f9..8e066155eecd83789548a398554b808c5cb2a5ed 100644 (file)
--- a/misoclib/tools/litescope/host/driver/pcie.py
+++ b/misoclib/tools/litescope/host/driver/pcie.py
@@ -21,10 +21,8 @@ class LiteScopePCIeDriver:
         self.mmap.close()
         self.f.close()
 
-    def read(self, addr, burst_length=None, repeats=None):
-        if repeats is not None:
-            raise NotImplementedError
-        values = []
+    def read(self, addr, burst_length=1):
+        datas = []
         for i in range(burst_length):
             self.mmap.seek(addr + 4*i)
             dat = self.mmap.read(4)
@@ -34,8 +32,11 @@ class LiteScopePCIeDriver:
             val |= dat[0] << 0
             if self.debug:
                 print("RD {:08X} @ {:08X}".format(val, addr + 4*i))
-            values.append(val)
-        return values
+            datas.append(val)
+        if burst_length == 1:
+            return datas[0]
+        else:
+            return datas
 
     def write(self, addr, data):
         if isinstance(data, list):
@@ -48,8 +49,8 @@ class LiteScopePCIeDriver:
             dat_bytes = [0, 0, 0, 0]
             dat_bytes[3] = (dat >> 24) & 0xff
             dat_bytes[2] = (dat >> 16) & 0xff
-            dat_bytes[1] = (dat >> 8) & 0xff
-            dat_bytes[0] = (dat >> 0) & 0xff
+            dat_bytes[1] = (dat >>  8) & 0xff
+            dat_bytes[0] = (dat >>  0) & 0xff
             self.mmap[addr + 4*i:addr + 4*(i+1)] = bytes(dat_bytes)
             if self.debug:
                 print("WR {:08X} @ {:08X}".format(dat, (addr + i)*4))

diff --git a/misoclib/tools/litescope/host/driver/reg.py b/misoclib/tools/litescope/host/driver/reg.py
index 2dc4d655a529ca0fdc4f603b0f506c46cdff6ca3..c101e23c761cb0398c9c5b5702c2bff4c57fe769 100644 (file)
--- a/misoclib/tools/litescope/host/driver/reg.py
+++ b/misoclib/tools/litescope/host/driver/reg.py
@@ -10,25 +10,19 @@ class MappedReg:
         self.busword = busword
         self.mode = mode
 
-    def read(self, repeats=None):
+    def read(self):
         if self.mode not in ["rw", "ro"]:
             raise KeyError(name + "register not readable")
-
-        def to_int(v):
-            return 1 if v is None else v
-        read_datas = self.readfn(self.addr, burst_length=self.length, repeats=repeats)
-        datas = []
-        for i in range(to_int(repeats)):
+        datas = self.readfn(self.addr, burst_length=self.length)
+        if isinstance(datas, int):
+            return datas
+        else:
             data = 0
-            for j in range(self.length):
+            for i in range(self.length):
                 data = data << self.busword
-                data |= read_datas[i*self.length+j]
-            datas.append(data)
-        if repeats is None:
-            return datas[0]
-        else:
-            return datas
-
+                data |= read_datas[i]
+            return data
+ 
     def write(self, value):
         if self.mode not in ["rw", "wo"]:
             raise KeyError(name + "register not writable")

diff --git a/misoclib/tools/litescope/host/driver/uart.py b/misoclib/tools/litescope/host/driver/uart.py
index b7f86e3c609d5f7871e25070d0efb6d2b8ff7e49..b1e42ead6188ff609f9e89b867f5752496d796e9 100644 (file)
--- a/misoclib/tools/litescope/host/driver/uart.py
+++ b/misoclib/tools/litescope/host/driver/uart.py
@@ -10,7 +10,7 @@ def write_b(uart, data):
 class LiteScopeUARTDriver:
     cmds = {
         "write": 0x01,
-        "read": 0x02
+        "read":  0x02
     }
     def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
         self.port = port
@@ -38,51 +38,46 @@ class LiteScopeUARTDriver:
         self.uart.flushOutput()
         self.uart.close()
 
-    def read(self, addr, burst_length=None, repeats=None):
+    def read(self, addr, burst_length=1):
         datas = []
-        def to_int(v):
-            return 1 if v is None else v
-        for i in range(to_int(repeats)):
-            self.uart.flushInput()
-            write_b(self.uart, self.cmds["read"])
-            write_b(self.uart, burst_length)
-            write_b(self.uart, (addr//4 & 0xff000000) >> 24)
-            write_b(self.uart, (addr//4 & 0x00ff0000) >> 16)
-            write_b(self.uart, (addr//4 & 0x0000ff00) >> 8)
-            write_b(self.uart, (addr//4 & 0x000000ff))
-            for j in range(to_int(burst_length)):
-                data = 0
-                for k in range(4):
-                    data = data << 8
-                    data |= ord(self.uart.read())
-                if self.debug:
-                    print("RD {:08X} @ {:08X}".format(data, (addr+j)*4))
-                datas.append(data)
-        return datas
+        self.uart.flushInput()
+        write_b(self.uart, self.cmds["read"])
+        write_b(self.uart, burst_length)
+        word_addr = addr//4
+        write_b(self.uart, (word_addr >> 24) & 0xff)
+        write_b(self.uart, (word_addr >> 16) & 0xff)
+        write_b(self.uart, (word_addr >>  8) & 0xff)
+        write_b(self.uart, (word_addr >>  0) & 0xff)
+        for i in range(burst_length):
+            data = 0
+            for k in range(4):
+                data = data << 8
+                data |= ord(self.uart.read())
+            if self.debug:
+                print("RD {:08X} @ {:08X}".format(data, addr + 4*i))
+            datas.append(data)
+        if burst_length == 1:
+            return datas[0]
+        else:
+            return datas
 
     def write(self, addr, data):
         if isinstance(data, list):
             burst_length = len(data)
         else:
             burst_length = 1
+            data = [data]
         write_b(self.uart, self.cmds["write"])
         write_b(self.uart, burst_length)
-        write_b(self.uart, (addr//4 & 0xff000000) >> 24)
-        write_b(self.uart, (addr//4 & 0x00ff0000) >> 16)
-        write_b(self.uart, (addr//4 & 0x0000ff00) >> 8)
-        write_b(self.uart, (addr//4 & 0x000000ff))
-        if isinstance(data, list):
-            for i in range(len(data)):
-                dat = data[i]
-                for j in range(4):
-                    write_b(self.uart, (dat & 0xff000000) >> 24)
-                    dat = dat << 8
-                if self.debug:
-                    print("WR {:08X} @ {:08X}".format(data[i], (addr + i)*4))
-        else:
-            dat = data
+        word_addr = addr//4
+        write_b(self.uart, (word_addr >> 24) & 0xff)
+        write_b(self.uart, (word_addr >> 16) & 0xff)
+        write_b(self.uart, (word_addr >>  8) & 0xff)
+        write_b(self.uart, (word_addr >>  0) & 0xff)
+        for i in range(len(data)):
+            dat = data[i]
             for j in range(4):
-                write_b(self.uart, (dat & 0xff000000) >> 24)
+                write_b(self.uart, (dat >> 24) & 0xff)
                 dat = dat << 8
             if self.debug:
-                print("WR {:08X} @ {:08X}".format(data, (addr * 4)))
+                print("WR {:08X} @ {:08X}".format(data[i], addr + 4*i))