Fix DAR/DSISR reading before they are written

If the DAR and DSISR are read before they are written, we assert with:

  register_file.vhdl:55:25:@60195ns:(report note): Writing GPR 09 00000000XXXXXXXX
  register_file.vhdl:61:17:@60195ns:(assertion failure): Assertion violation

This initialises DAR/DSISR to avoid this.

Signed-off-by: Michael Neuling <mikey@neuling.org>

diff --git a/loadstore1.vhdl b/loadstore1.vhdl
index ee4507b15a30736bf84645978f78bad39dff1ddd..33286170c2167a6fbee1c731dc1b8a7cf2a0976f 100644 (file)
--- a/loadstore1.vhdl
+++ b/loadstore1.vhdl
@@ -275,6 +275,8 @@ begin
                 r2.wait_dc <= '0';
                 r2.wait_mmu <= '0';
                 r2.one_cycle <= '0';
+                r3.dar <= (others => '0');
+                r3.dsisr <= (others => '0');
                 r3.state <= IDLE;
                 r3.write_enable <= '0';
                 r3.interrupt <= '0';