ARM: Add support for switching CPUs

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index c7c00924d9f62d5322a773a898b08c619f69f7ed..98dc1760d1f97659ab11700c811e4739bf253c3d 100644 (file)
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -43,6 +43,7 @@
 #include "dev/io_device.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "sim/system.hh"
 
 using namespace ArmISA;
 
@@ -59,9 +60,10 @@ TableWalker::~TableWalker()
 }
 
 
-unsigned int TableWalker::drain(Event *de)
+unsigned int
+TableWalker::drain(Event *de)
 {
-    if (stateQueueL1.size() != 0 || stateQueueL2.size() != 0)
+    if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size())
     {
         changeState(Draining);
         DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n");
@@ -75,6 +77,16 @@ unsigned int TableWalker::drain(Event *de)
     }
 }
 
+void
+TableWalker::resume()
+{
+    MemObject::resume();
+    if ((params()->sys->getMemoryMode() == Enums::timing) && currState) {
+            delete currState;
+            currState = NULL;
+    }
+}
+
 Port*
 TableWalker::getPort(const std::string &if_name, int idx)
 {

diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 0804997c309706a898309b1531318d4d62366df5..2739973e8e78303366e12ccd8f085dec63913030 100644 (file)
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -351,6 +351,7 @@ class TableWalker : public MemObject
     }
 
     virtual unsigned int drain(Event *de);
+    virtual void resume();
     virtual Port *getPort(const std::string &if_name, int idx = -1);
 
     Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,

diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index a114ec5e0705e8dfa9a82ebc067409cb9959ca68..c42a8dddd9498d152c47cb5ace4178113aa70f96 100644 (file)
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -133,5 +133,22 @@ skipFunction(ThreadContext *tc)
     tc->pcState(newPC);
 }
 
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    int i;
+    for(i = 0; i < TheISA::NumIntRegs; i++)
+        dest->setIntReg(i, src->readIntReg(i));
+    for(i = 0; i < TheISA::NumFloatRegs; i++)
+        dest->setFloatReg(i, src->readFloatReg(i));
+    for(i = 0; i < TheISA::NumMiscRegs; i++)
+        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 
+    // setMiscReg "with effect" will set the misc register mapping correctly.
+    // e.g. updateRegMap(val)
+    dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
+
+    // Lastly copy PC/NPC
+    dest->pcState(src->pcState());
+}
 }

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index a92ab072c74d283d6ef87a5dd9d33a5752e8f079..ca54984cb0a71caa473cde8feef834039765c2a6 100644 (file)
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -102,11 +102,7 @@ namespace ArmISA {
         tc->activate(0);
     }
 
-    static inline void
-    copyRegs(ThreadContext *src, ThreadContext *dest)
-    {
-        panic("Copy Regs Not Implemented Yet\n");
-    }
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     static inline void
     copyMiscRegs(ThreadContext *src, ThreadContext *dest)