Use new -wb flag for ABC flow

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 582c49976df683c6a1f089a6046fe67a56f3a4d3..975780488d146522dbc3ebad5a7980f8b66c0353 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -103,7 +103,7 @@ struct XAigerWriter
                return aig_map.at(bit);
        }
 
-       XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
+       XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool ignore_boxes=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
        {
                pool<SigBit> undriven_bits;
                pool<SigBit> unused_bits;
@@ -177,36 +177,38 @@ struct XAigerWriter
 
                for (auto cell : module->cells())
                {
-                       toposort.node(cell->name);
-                       for (const auto &conn : cell->connections())
-                       {
-                               if (!cell->type.in("$_NOT_", "$_AND_")) {
-                                       if (yosys_celltypes.cell_known(cell->type)) {
-                                               if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
-                                                       continue;
-                                               if (cell->type == "$memrd" && conn.first == "\\DATA")
+                       if (!ignore_boxes) {
+                               toposort.node(cell->name);
+                               for (const auto &conn : cell->connections())
+                               {
+                                       if (!cell->type.in("$_NOT_", "$_AND_")) {
+                                               if (yosys_celltypes.cell_known(cell->type)) {
+                                                       if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
+                                                               continue;
+                                                       if (cell->type == "$memrd" && conn.first == "\\DATA")
+                                                               continue;
+                                               }
+
+                                               RTLIL::Module* inst_module = module->design->module(cell->type);
+                                               log_assert(inst_module);
+                                               RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
+                                               log_assert(inst_module_port);
+
+                                               if (inst_module_port->attributes.count("\\abc_flop_q"))
                                                        continue;
                                        }
 
-                                       RTLIL::Module* inst_module = module->design->module(cell->type);
-                                       log_assert(inst_module);
-                                       RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
-                                       log_assert(inst_module_port);
-
-                                       if (inst_module_port->attributes.count("\\abc_flop_q"))
-                                               continue;
-                               }
+                                       if (cell->input(conn.first)) {
+                                               // Ignore inout for the sake of topographical ordering
+                                               if (cell->output(conn.first)) continue;
+                                               for (auto bit : sigmap(conn.second))
+                                                       bit_users[bit].insert(cell->name);
+                                       }
 
-                               if (cell->input(conn.first)) {
-                                       // Ignore inout for the sake of topographical ordering
-                                       if (cell->output(conn.first)) continue;
-                                       for (auto bit : sigmap(conn.second))
-                                               bit_users[bit].insert(cell->name);
+                                       if (cell->output(conn.first))
+                                               for (auto bit : sigmap(conn.second))
+                                                       bit_drivers[bit].insert(cell->name);
                                }
-
-                               if (cell->output(conn.first))
-                                       for (auto bit : sigmap(conn.second))
-                                               bit_drivers[bit].insert(cell->name);
                        }
 
                        if (cell->type == "$_NOT_")
@@ -249,7 +251,7 @@ struct XAigerWriter
                        //      continue;
                        //}
 
-                       RTLIL::Module* box_module = module->design->module(cell->type);
+                       RTLIL::Module* box_module = !ignore_boxes ? module->design->module(cell->type) : nullptr;
                        if (!box_module || !box_module->attributes.count("\\abc_box_id")) {
                                for (const auto &c : cell->connections()) {
                                        if (c.second.is_fully_const()) continue;
@@ -705,12 +707,12 @@ struct XAigerWriter
                                RTLIL::Selection& sel = holes_module->design->selection_stack.back();
                                sel.select(holes_module);
 
-                               Pass::call(holes_module->design, "flatten; aigmap");
+                               Pass::call(holes_module->design, "flatten -wb; aigmap");
 
                                holes_module->design->selection_stack.pop_back();
 
                                std::stringstream a_buffer;
-                               XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/);
+                               XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/, true /* ignore_boxes */);
                                writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/);
 
                                f << "a";

diff --git a/techlibs/ice40/abc.v b/techlibs/ice40/abc.v
deleted file mode 100644 (file)
index e2a54a4..0000000
--- a/techlibs/ice40/abc.v
+++ /dev/null
@@ -1,12 +0,0 @@
-(* abc_box_id = 1 *)
-module SB_CARRY (output CO, input CI, I0, I1);
-       assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
-
-(* abc_box_id = 2 *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
-       parameter [15:0] LUT_INIT = 0;
-       // Indicate this is a black-box
-       assign O = 1'b0;
-endmodule
-

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 70cd51ed10a5662d4121c74881b07807809a9086..dba563e370ed373c5fafc97270cc6842e714a33a 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,6 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
+(* abc_box_id = 2 *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
        parameter [15:0] LUT_INIT = 0;
        wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -126,6 +127,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
        assign O = I0 ? s1[1] : s1[0];
 endmodule
 
+(* abc_box_id = 1, whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
        assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7c95588e4d8159ea5be574797923bf07c1a831ff..84abf71819558ea7062e1ba0719f501a482c529a 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
        {
                if (check_label("begin"))
                {
-                       run("read_verilog -lib +/ice40/cells_sim.v");
+                       run("read_verilog -wb +/ice40/cells_sim.v");
                        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
                        run("proc");
                }
@@ -327,12 +327,8 @@ struct SynthIce40Pass : public ScriptPass
                                run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
                        }
                        if (!noabc) {
-                               if (abc == "abc9") {
-                                       run("read_verilog +/ice40/abc.v");
-                                       run("techmap -map +/techmap.v A:abc_box_id");
-                                       run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
-                                       run("blackbox A:abc_box_id");
-                               }
+                               if (abc == "abc9")
+                                       run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
                                else
                                        run(abc + " -lut 4", "(skip if -noabc)");
                        }