bool flag_make_outputs = false;
bool flag_make_outcmp = false;
bool flag_make_assert = false;
+ bool flag_flatten = false;
log_header("Executing MITER pass (creating miter circuit).\n");
flag_make_assert = true;
continue;
}
+ if (args[argidx] == "-flatten") {
+ flag_flatten = true;
+ continue;
+ }
break;
}
if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-")
miter_module->add(not_cell);
miter_module->fixup_ports();
+
+ if (flag_flatten) {
+ log_push();
+ Pass::call_on_module(design, miter_module, "flatten; opt_const -undriven;;");
+ log_pop();
+ }
}
struct MiterPass : public Pass {
log(" -make_assert\n");
log(" also create an 'assert' cell that checks if trigger is always low.\n");
log("\n");
+ log(" -flatten\n");
+ log(" call 'flatten; opt_const -undriven;;' on the miter circuit.\n");
+ log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
print('copy uut_%05d gold' % idx)
print('rename uut_%05d gate' % idx)
print('share -aggressive gate')
- print('miter -equiv -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
- print('flatten miter')
+ print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
print('sat -verify -prove trigger 0 -show-inputs -show-outputs miter')