mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
authorHoa Nguyen <hoanguyen@ucdavis.edu>
Fri, 20 Nov 2020 01:45:07 +0000 (17:45 -0800)
committerHoa Nguyen <hoanguyen@ucdavis.edu>
Tue, 22 Dec 2020 09:52:36 +0000 (09:52 +0000)
This change moves some stats that are used in SLICC to a
separate Stats::Group.

In order to use stats in SLICC, new functions are added in
CacheMemory:
        - profileDemandHit()
        - profileDemandMiss()

The functions increase the corresponding stat by 1.

Change-Id: I52b6fefdf6579a49f626f2fca400641f90800017
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37815
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

19 files changed:
src/mem/ruby/protocol/GPU_VIPER-TCC.sm
src/mem/ruby/protocol/GPU_VIPER-TCP.sm
src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
src/mem/ruby/protocol/MESI_Three_Level_HTM-L0cache.sm
src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
src/mem/ruby/protocol/MI_example-cache.sm
src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
src/mem/ruby/protocol/MOESI_hammer-cache.sm
src/mem/ruby/protocol/RubySlicc_Types.sm
src/mem/ruby/structures/CacheMemory.cc
src/mem/ruby/structures/CacheMemory.hh

index c4c4c3e06eee062a9320822b73d72d94d84b127f..5edd7dbba3b10b92938fa624c4916c0205a2871c 100644 (file)
@@ -439,11 +439,11 @@ machine(MachineType:TCC, "TCC Cache")
   }
 
   action(p_profileMiss, "pm", desc="Profile cache miss") {
-      ++L2cache.demand_misses;
+      L2cache.profileDemandMiss();
   }
 
   action(p_profileHit, "ph", desc="Profile cache hit") {
-      ++L2cache.demand_hits;
+      L2cache.profileDemandHit();
   }
 
   action(t_allocateTBE, "t", desc="allocate TBE Entry") {
index aafe5a4118d62e4c217695246d35ce8d8d81cf2a..5e987c8e821e67f6cd4a1b2603ff817ba165b7f6 100644 (file)
@@ -529,11 +529,11 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
 
   // added for profiling
   action(uu_profileDataMiss, "\udm", desc="Profile the demand miss"){
-      ++L1cache.demand_misses;
+    L1cache.profileDemandMiss();
   }
 
   action(uu_profileDataHit, "\udh", desc="Profile the demand hit"){
-      ++L1cache.demand_hits;
+    L1cache.profileDemandHit();
   }
 
 
index 4de4a293e07542afb9f6f77f84d20c84c3296bfb..46c1664c0d575dc1c53076fc0161cec0ab64be91 100644 (file)
@@ -771,19 +771,19 @@ machine(MachineType:L0Cache, "MESI Directory L0 Cache")
   }
 
   action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
-        ++Icache.demand_misses;
+    Icache.profileDemandMiss();
   }
 
   action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
-        ++Icache.demand_hits;
+    Icache.profileDemandHit();
   }
 
   action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
-        ++Dcache.demand_misses;
+    Dcache.profileDemandMiss();
   }
 
   action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
-        ++Dcache.demand_hits;
+    Dcache.profileDemandHit();
   }
 
   // store conditionals
index 7344ca1d2b870cc17c2901e9d5b42c36af14ff68..bcf99ff362659d295a3985c8139acfcaf9121940 100644 (file)
@@ -774,11 +774,11 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
   }
 
   action(uu_profileMiss, "\um", desc="Profile the demand miss") {
-      ++cache.demand_misses;
+    cache.profileDemandMiss();
   }
 
   action(uu_profileHit, "\uh", desc="Profile the demand hit") {
-      ++cache.demand_hits;
+    cache.profileDemandHit();
   }
 
 
index a6e4fafb5e4f10104ba53b849b94cd4a1137a710..4d5935dc9bdf0b3ec313711987042c37caa16575 100644 (file)
@@ -915,19 +915,19 @@ machine(MachineType:L0Cache, "MESI Directory L0 Cache")
   }
 
   action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
-        ++Icache.demand_misses;
+    Icache.profileDemandMiss();
   }
 
   action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
-        ++Icache.demand_hits;
+    Icache.profileDemandHit();
   }
 
   action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
-        ++Dcache.demand_misses;
+    Dcache.profileDemandMiss();
   }
 
   action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
-        ++Dcache.demand_hits;
+    Dcache.profileDemandHit();
   }
 
   // store conditionals
index 3e07e03024fdb7f95d0999961f08186a57047172..1a5d0e5b12cfa8927c90b9f9c10bccd57140b3a4 100644 (file)
@@ -956,19 +956,19 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
   }
 
   action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
-      ++L1Icache.demand_misses;
+    L1Icache.profileDemandMiss();
   }
 
   action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
-      ++L1Icache.demand_hits;
+    L1Icache.profileDemandHit();
   }
 
   action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
-      ++L1Dcache.demand_misses;
+    L1Dcache.profileDemandMiss();
   }
 
   action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
-      ++L1Dcache.demand_hits;
+    L1Dcache.profileDemandHit();
   }
 
   action(po_observeHit, "\ph", desc="Inform the prefetcher about the hit") {
index 91f58ff6a4312f22d8de1a7a52f9452fbae48c31..b189f71cab3bd3cc30ba0026b6232921d0f0b181 100644 (file)
@@ -732,11 +732,11 @@ machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP")
   }
 
   action(uu_profileMiss, "\um", desc="Profile the demand miss") {
-      ++L2cache.demand_misses;
+    L2cache.profileDemandMiss();
   }
 
   action(uu_profileHit, "\uh", desc="Profile the demand hit") {
-      ++L2cache.demand_hits;
+    L2cache.profileDemandHit();
   }
 
   action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
index 2c9bdb789a7d14bccfdf2e62eebe46352b6a19e6..e662a76a870d6e60ed2c4b4bd0f19f8b16c652f8 100644 (file)
@@ -350,11 +350,11 @@ machine(MachineType:L1Cache, "MI Example L1 Cache")
   }
 
   action(p_profileMiss, "pi", desc="Profile cache miss") {
-      ++cacheMemory.demand_misses;
+    cacheMemory.profileDemandMiss();
   }
 
   action(p_profileHit, "ph", desc="Profile cache hit") {
-      ++cacheMemory.demand_hits;
+    cacheMemory.profileDemandHit();
   }
 
   action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
index fb957f087281d657bdfe3543c5e0e52985131b45..11b53bcdf7d42f16c0e1e87014ec80a52b616598 100644 (file)
@@ -1267,35 +1267,35 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
   }
 
   action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
-    ++L2cache.demand_misses;
+    L2cache.profileDemandMiss();
   }
 
   action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
-    ++L1D0cache.demand_misses;
+    L1D0cache.profileDemandMiss();
   }
 
   action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
-    ++L1D1cache.demand_misses;
+    L1D1cache.profileDemandMiss();
   }
 
   action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
-    ++L1Icache.demand_misses;
+    L1Icache.profileDemandMiss();
   }
 
   action(l10h_profileHit, "l10h", desc="l10h hit profile") {
-    ++L1D0cache.demand_hits;
+    L1D0cache.profileDemandHit();
   }
 
   action(l11h_profileHit, "l11h", desc="l11h hit profile") {
-    ++L1D1cache.demand_hits;
+    L1D1cache.profileDemandHit();
   }
 
   action(l1ih_profileHit, "l1lh", desc="l1ih hit profile") {
-    ++L1Icache.demand_hits;
+    L1Icache.profileDemandHit();
   }
 
   action(l2h_profileHit, "l2h", desc="l2h hit profile") {
-    ++L2cache.demand_hits;
+    L2cache.profileDemandHit();
   }
 
   action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
index 3f24d5ab19fb310eeec13c70944cf0e6a98a1f43..d4c6bbc8d6de93ea79171b01c1a9fdcd1c50f62a 100644 (file)
@@ -1421,19 +1421,19 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
   }
 
   action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
-    ++L1D0cache.demand_misses;
+    L1D0cache.profileDemandMiss();
   }
 
   action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
-    ++L1D1cache.demand_misses;
+    L1D1cache.profileDemandMiss();
   }
 
   action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
-    ++L1Icache.demand_misses;
+    L1Icache.profileDemandMiss();
   }
 
   action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
-    ++L2cache.demand_misses;
+    L2cache.profileDemandMiss();
   }
 
   action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
index 389d1237fd998ec61b477cb375eee6e5c67ea224..684d03e3ce7bebabf756fbb7108a92a0a0a91dd3 100644 (file)
@@ -639,9 +639,9 @@ machine(MachineType:Directory, "AMD Baseline protocol")
   //deallocated in dt_deallocateTBE (only for WB) as it checks the L3Hit flag of the TBE entry.
   action(pr_profileL3HitMiss, "pr_l3hm", desc="L3 Hit or Miss Profile") {
     if (tbe.L3Hit) {
-      ++L3CacheMemory.demand_hits;
+      L3CacheMemory.profileDemandHit();
     } else {
-      ++L3CacheMemory.demand_misses;
+      L3CacheMemory.profileDemandMiss();
     }
   }
 
index 15bbdd3f2898c6cbd7532ed2d9e818f6113151fc..edd1435bead76f51b62c37970612e32dbf9e6aec 100644 (file)
@@ -905,19 +905,19 @@ machine(MachineType:L1Cache, "L1 cache protocol")
   }
 
   action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
-      ++L1Icache.demand_misses;
+    L1Icache.profileDemandMiss();
   }
 
   action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
-      ++L1Icache.demand_hits;
+    L1Icache.profileDemandHit();
   }
 
   action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
-      ++L1Dcache.demand_misses;
+    L1Dcache.profileDemandMiss();
   }
 
   action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
-      ++L1Dcache.demand_hits;
+    L1Dcache.profileDemandHit();
   }
 
   action(z_recycleRequestQueue, "z", desc="Send the head of the mandatory queue to the back of the queue.") {
index 989410768bc947ac11c838aabe89749e28b3c5b9..b11187911382fe940f95a6da9854246e356c6afc 100644 (file)
@@ -1560,11 +1560,11 @@ machine(MachineType:L2Cache, "Token protocol")
   }
 
   action(uu_profileMiss, "\um", desc="Profile the demand miss") {
-      ++L2cache.demand_misses;
+    L2cache.profileDemandMiss();
   }
 
   action(uu_profileHit, "\uh", desc="Profile the demand hit") {
-      ++L2cache.demand_hits;
+    L2cache.profileDemandHit();
   }
 
   action(y_copyCacheStateToDir, "y", desc="Copy cache state to directory state") {
index 17c518a102e0a308cac320bf6bffbf860901c444..5c3d5f79d1290e30484b59f32d51126731cf02be 100644 (file)
@@ -1549,19 +1549,19 @@ machine(MachineType:L1Cache, "Token protocol")
   }
 
   action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
-      ++L1Icache.demand_misses;
+    L1Icache.profileDemandMiss();
   }
 
   action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
-      ++L1Icache.demand_hits;
+    L1Icache.profileDemandHit();
   }
 
   action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
-      ++L1Dcache.demand_misses;
+    L1Dcache.profileDemandMiss();
   }
 
   action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
-      ++L1Dcache.demand_hits;
+    L1Dcache.profileDemandHit();
   }
 
   action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {
index 119508aa80aefe2bef80b02ac3c860c452b5d3ae..2f8623a0c4d95608e134c639c49e68f78030af1b 100644 (file)
@@ -981,11 +981,11 @@ machine(MachineType:L2Cache, "Token protocol")
   }
 
   action(uu_profileMiss, "\um", desc="Profile the demand miss") {
-      ++L2cache.demand_misses;
+    L2cache.profileDemandMiss();
   }
 
   action(uu_profileHit, "\uh", desc="Profile the demand hit") {
-      ++L2cache.demand_hits;
+    L2cache.profileDemandHit();
   }
 
   action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {
index 5440eb8e2f6f3d61f90c202b8330f39b7e15e8f3..aba28fff7c81ef756aff4c064212c704a080c756 100644 (file)
@@ -1266,27 +1266,27 @@ machine(MachineType:L1Cache, "AMD Hammer-like protocol")
   }
 
   action(uu_profileL1DataMiss, "\udm", desc="Profile the demand miss") {
-      ++L1Dcache.demand_misses;
+    L1Dcache.profileDemandMiss();
   }
 
   action(uu_profileL1DataHit, "\udh", desc="Profile the demand hits") {
-      ++L1Dcache.demand_hits;
+    L1Dcache.profileDemandHit();
   }
 
   action(uu_profileL1InstMiss, "\uim", desc="Profile the demand miss") {
-      ++L1Icache.demand_misses;
+    L1Icache.profileDemandMiss();
   }
 
   action(uu_profileL1InstHit, "\uih", desc="Profile the demand hits") {
-      ++L1Icache.demand_hits;
+    L1Icache.profileDemandHit();
   }
 
   action(uu_profileL2Miss, "\um", desc="Profile the demand miss") {
-      ++L2cache.demand_misses;
+    L2cache.profileDemandMiss();
   }
 
   action(uu_profileL2Hit, "\uh", desc="Profile the demand hits") {
-      ++L2cache.demand_hits;
+    L2cache.profileDemandHit();
   }
 
   action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
index af7c0170b5736e7f3b1e8bb4598ac341a72911c2..d085fde139137a7c78fd21ed7e9d9223c1005e61 100644 (file)
@@ -211,8 +211,8 @@ structure (CacheMemory, external = "yes") {
   int getNumBlocks();
   Addr getAddressAtIdx(int);
 
-  Scalar demand_misses;
-  Scalar demand_hits;
+  void profileDemandHit();
+  void profileDemandMiss();
 }
 
 structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
index 3a27f8e6ba310a70fc2f7856c4dfc4c8e2c1c5d5..4c04fd7a56ed825d77edc417cbe487cf655d9444 100644 (file)
@@ -68,16 +68,7 @@ CacheMemory::CacheMemory(const Params &p)
               p.start_index_bit, p.ruby_system),
     tagArray(p.tagArrayBanks, p.tagAccessLatency,
              p.start_index_bit, p.ruby_system),
-    cacheMemoryStats(this),
-    ADD_STAT(m_demand_hits, "Number of cache demand hits"),
-    ADD_STAT(m_demand_misses, "Number of cache demand misses"),
-    ADD_STAT(m_demand_accesses, "Number of cache demand accesses",
-                                  m_demand_hits + m_demand_misses),
-    ADD_STAT(m_sw_prefetches, "Number of software prefetches"),
-    ADD_STAT(m_hw_prefetches, "Number of hardware prefetches"),
-    ADD_STAT(m_prefetches, "Number of prefetches",
-                          m_sw_prefetches + m_hw_prefetches),
-    ADD_STAT(m_accessModeType, "")
+    cacheMemoryStats(this)
 {
     m_cache_size = p.size;
     m_cache_assoc = p.assoc;
@@ -88,26 +79,6 @@ CacheMemory::CacheMemory(const Params &p)
     m_block_size = p.block_size;  // may be 0 at this point. Updated in init()
     m_use_occupancy = dynamic_cast<ReplacementPolicy::WeightedLRU*>(
                                     m_replacementPolicy_ptr) ? true : false;
-
-    m_sw_prefetches
-        .flags(Stats::nozero);
-
-    m_hw_prefetches
-        .flags(Stats::nozero);
-
-    m_prefetches
-        .flags(Stats::nozero);
-
-    m_accessModeType
-        .init(RubyRequestType_NUM)
-        .flags(Stats::pdf | Stats::total);
-
-    for (int i = 0; i < RubyAccessMode_NUM; i++) {
-        m_accessModeType
-            .subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
-            .flags(Stats::nozero)
-            ;
-    }
 }
 
 void
@@ -559,7 +530,16 @@ CacheMemoryStats::CacheMemoryStats(Stats::Group *parent)
                                        "transaction"),
       ADD_STAT(htmTransAbortReadSet, "Read set size of a aborted transaction"),
       ADD_STAT(htmTransAbortWriteSet, "Write set size of a aborted "
-                                      "transaction")
+                                      "transaction"),
+      ADD_STAT(m_demand_hits, "Number of cache demand hits"),
+      ADD_STAT(m_demand_misses, "Number of cache demand misses"),
+      ADD_STAT(m_demand_accesses, "Number of cache demand accesses",
+               m_demand_hits + m_demand_misses),
+      ADD_STAT(m_sw_prefetches, "Number of software prefetches"),
+      ADD_STAT(m_hw_prefetches, "Number of hardware prefetches"),
+      ADD_STAT(m_prefetches, "Number of prefetches",
+               m_sw_prefetches + m_hw_prefetches),
+      ADD_STAT(m_accessModeType, "")
 {
     numDataArrayReads
         .flags(Stats::nozero);
@@ -595,6 +575,25 @@ CacheMemoryStats::CacheMemoryStats(Stats::Group *parent)
         .init(8)
         .flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan);
 
+    m_sw_prefetches
+        .flags(Stats::nozero);
+
+    m_hw_prefetches
+        .flags(Stats::nozero);
+
+    m_prefetches
+        .flags(Stats::nozero);
+
+    m_accessModeType
+        .init(RubyRequestType_NUM)
+        .flags(Stats::pdf | Stats::total);
+
+    for (int i = 0; i < RubyAccessMode_NUM; i++) {
+        m_accessModeType
+            .subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
+            .flags(Stats::nozero)
+            ;
+    }
 }
 
 // assumption: SLICC generated files will only call this function
@@ -738,3 +737,15 @@ CacheMemory::htmCommitTransaction()
     DPRINTF(HtmMem, "htmCommitTransaction: read set=%u write set=%u\n",
         htmReadSetSize, htmWriteSetSize);
 }
+
+void
+CacheMemory::profileDemandHit()
+{
+    cacheMemoryStats.m_demand_hits++;
+}
+
+void
+CacheMemory::profileDemandMiss()
+{
+    cacheMemoryStats.m_demand_misses++;
+}
\ No newline at end of file
index c126a535db01acca6444360dc35dab96aaff1fa3..84b9d87817e3d95a1833274679c81287a3240782 100644 (file)
@@ -148,25 +148,6 @@ class CacheMemory : public SimObject
     void htmCommitTransaction();
 
   public:
-    struct CacheMemoryStats : public Stats::Group
-    {
-        CacheMemoryStats(Stats::Group *parent);
-
-        Stats::Scalar numDataArrayReads;
-        Stats::Scalar numDataArrayWrites;
-        Stats::Scalar numTagArrayReads;
-        Stats::Scalar numTagArrayWrites;
-
-        Stats::Scalar numTagArrayStalls;
-        Stats::Scalar numDataArrayStalls;
-
-        // hardware transactional memory
-        Stats::Histogram htmTransCommitReadSet;
-        Stats::Histogram htmTransCommitWriteSet;
-        Stats::Histogram htmTransAbortReadSet;
-        Stats::Histogram htmTransAbortWriteSet;
-    };
-
     int getCacheSize() const { return m_cache_size; }
     int getCacheAssoc() const { return m_cache_assoc; }
     int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
@@ -224,17 +205,41 @@ class CacheMemory : public SimObject
      */
     bool m_use_occupancy;
 
-    public:
-      CacheMemoryStats cacheMemoryStats;
-      Stats::Scalar m_demand_hits;
-      Stats::Scalar m_demand_misses;
-      Stats::Formula m_demand_accesses;
+    private:
+      struct CacheMemoryStats : public Stats::Group
+      {
+          CacheMemoryStats(Stats::Group *parent);
 
-      Stats::Scalar m_sw_prefetches;
-      Stats::Scalar m_hw_prefetches;
-      Stats::Formula m_prefetches;
+          Stats::Scalar numDataArrayReads;
+          Stats::Scalar numDataArrayWrites;
+          Stats::Scalar numTagArrayReads;
+          Stats::Scalar numTagArrayWrites;
 
-      Stats::Vector m_accessModeType;
+          Stats::Scalar numTagArrayStalls;
+          Stats::Scalar numDataArrayStalls;
+
+          // hardware transactional memory
+          Stats::Histogram htmTransCommitReadSet;
+          Stats::Histogram htmTransCommitWriteSet;
+          Stats::Histogram htmTransAbortReadSet;
+          Stats::Histogram htmTransAbortWriteSet;
+
+          Stats::Scalar m_demand_hits;
+          Stats::Scalar m_demand_misses;
+          Stats::Formula m_demand_accesses;
+
+          Stats::Scalar m_sw_prefetches;
+          Stats::Scalar m_hw_prefetches;
+          Stats::Formula m_prefetches;
+
+          Stats::Vector m_accessModeType;
+      } cacheMemoryStats;
+
+    public:
+      // These function increment the number of demand hits/misses by one
+      // each time they are called
+      void profileDemandHit();
+      void profileDemandMiss();
 };
 
 std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);