replacing setvl-svstep with just svstep

diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py
index 7612b5c6c0927a9a7f39f5a95803d359ba61b337..bfc7a5b6e84e7ddbbfd4e9ab8de258b4c62e7434 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svstate.py
+++ b/src/openpower/decoder/isa/test_caller_svstate.py
@@ -68,10 +68,10 @@ class SVSTATETestCase(FHDLTestCase):
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add 1, *5, *9',
                         'sv.addi *12, 1, 1',
-                        "setvl. 0, 0, 1, 1, 0, 0",
+                        "svstep. 0, 1, 0",
                         'sv.add 1, *5, *9',
                         'sv.addi *12, 1, 1',
-                        "setvl. 0, 0, 1, 1, 0, 0"
+                        "svstep. 0, 1, 0",
                         ])
 
         sequence is as follows:
@@ -100,10 +100,10 @@ class SVSTATETestCase(FHDLTestCase):
         lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1",
                         'sv.add 1, *5, *9',       # scalar dest (into r1)
                         'sv.addi *12, 1, 1',       # scalar src (from r1)
-                        "setvl. 0, 0, 1, 1, 0, 0",  # svstep
+                        "svstep. 0, 1, 0",  # svstep
                         'sv.add 1, *5, *9',       # again, scalar dest
                         'sv.addi *12, 1, 1',       # but vector dest
-                        "setvl. 0, 0, 1, 1, 0, 0"  # svstep (end: sets CR0.SO)
+                        "svstep. 0, 1, 0",  # svstep (end: sets CR0.SO)
                         ])
         lst = list(lst)