vendor.xilinx_{7series,ultrascale}: hierachical -> hierarchical

Signed-off-by: Robin Ole Heinemann <robin.ole.heinemann@gmail.com>

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index c0f7daeb2f6ceee14f2f86859ea84636c2545cd4..cfb1b442a16fd6da3ec0b460758eaa6b188ef086 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -122,7 +122,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             }
             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
             report_timing_summary -file {{name}}_timing_synth.rpt
-            report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
+            report_utilization -hierarchical -file {{name}}_utilization_hierarchical_synth.rpt
             report_utilization -file {{name}}_utilization_synth.rpt
             opt_design
             place_design

diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index bc28ac28a5c0d3c06ec39571e17155aa304df860..1a2d3913391dc637bcf2a68cf4fc8ef7bd4884cf 100644 (file)
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -96,7 +96,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
             }
             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
             report_timing_summary -file {{name}}_timing_synth.rpt
-            report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
+            report_utilization -hierarchical -file {{name}}_utilization_hierarchical_synth.rpt
             report_utilization -file {{name}}_utilization_synth.rpt
             opt_design
             place_design