fprintf(f, ".names $true\n1\n");
}
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if(cell_id == curr_cell)
break;
log(" -- found cell %s\n", cstr(cell_id));
- RTLIL::Cell* cell = module->cells.at(cell_id);
+ RTLIL::Cell* cell = module->cells_.at(cell_id);
const RTLIL::SigSpec* cell_output = get_cell_output(cell);
int cell_line = dump_cell(cell);
log("creating intermediate wires map\n");
//creating map of intermediate wires as output of some cell
- for (auto it = module->cells.begin(); it != module->cells.end(); ++it)
+ for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it)
{
RTLIL::Cell *cell = it->second;
const RTLIL::SigSpec* output_sig = get_cell_output(cell);
}
log("writing cells\n");
- for(auto cell_it = module->cells.begin(); cell_it != module->cells.end(); ++cell_it)
+ for(auto cell_it = module->cells_.begin(); cell_it != module->cells_.end(); ++cell_it)
{
dump_cell(cell_it->second);
}
if (module->memories.size() != 0)
log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
- for (auto cell_it : module->cells)
+ for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
for (auto &mod_it : design->modules) {
module_deps[mod_it.second] = std::set<RTLIL::Module*>();
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
if (design->modules.count(cell_it.second->type) > 0)
module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type));
}
fprintf(f, " (contents\n");
fprintf(f, " (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
fprintf(f, " (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
fprintf(f, " (instance %s\n", EDIF_DEF(cell->name));
fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
dump_memory(f, indent + " ", it->second);
}
- for (auto it = module->cells.begin(); it != module->cells.end(); it++)
+ for (auto it = module->cells_.begin(); it != module->cells_.end(); it++)
if (!only_selected || design->selected(module, it->second)) {
if (only_selected)
fprintf(f, "\n");
if (module->get_bool_attribute("\\blackbox"))
continue;
- if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
+ if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0)
continue;
if (selected && !design->selected_whole_module(module->name)) {
}
// Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
- for (auto cell_it : module->cells)
+ for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
std::string celltype_code, node_code;
SigMap sigmap(module);
int cell_counter = 0, conn_counter = 0, nc_counter = 0;
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
fprintf(f, "X%d", cell_counter++);
for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
reset_auto_counter_id(it->second->name, true);
- for (auto it = module->cells.begin(); it != module->cells.end(); it++) {
+ for (auto it = module->cells_.begin(); it != module->cells_.end(); it++) {
reset_auto_counter_id(it->second->name, true);
reset_auto_counter_id(it->second->type, false);
}
if (!noexpr)
{
std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q"))
for (auto it = module->memories.begin(); it != module->memories.end(); it++)
dump_memory(f, indent + " ", it->second);
- for (auto it = module->cells.begin(); it != module->cells.end(); it++)
+ for (auto it = module->cells_.begin(); it != module->cells_.end(); it++)
dump_cell(f, indent + " ", it->second);
for (auto it = module->processes.begin(); it != module->processes.end(); it++)
{
rerun_invert_rollback = false;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (it.second->type == "$_INV_" && it.second->get("\\Y") == clk_sig) {
clk_sig = it.second->get("\\A");
clk_polarity = !clk_polarity;
{
rerun_invert_rollback = false;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (it.second->type == "$_INV_" && it.second->get("\\Y") == enable_sig) {
enable_sig = it.second->get("\\A");
enable_polarity = !enable_polarity;
ct.setup_internals();
ct.setup_stdcells();
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (!ct.cell_known(it.second->type))
continue;
for (auto &it2 : it.second->connections())
if (RTLIL::unescape_id(it.first).substr(0, len) == text)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (RTLIL::unescape_id(it.first).substr(0, len) == text)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
for (auto &it : module->wires_)
add_wire(it.second);
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (filter_ct == NULL || filter_ct->cell_known(it.second->type))
add_cell(it.second);
}
if (it.second.size() == 0)
del_list.push_back(it.first);
else if (it.second.size() == design->modules[it.first]->wires_.size() + design->modules[it.first]->memories.size() +
- design->modules[it.first]->cells.size() + design->modules[it.first]->processes.size())
+ design->modules[it.first]->cells_.size() + design->modules[it.first]->processes.size())
add_list.push_back(it.first);
for (auto mod_name : del_list)
selected_members.erase(mod_name);
delete it->second;
for (auto it = memories.begin(); it != memories.end(); it++)
delete it->second;
- for (auto it = cells.begin(); it != cells.end(); it++)
+ for (auto it = cells_.begin(); it != cells_.end(); it++)
delete it->second;
for (auto it = processes.begin(); it != processes.end(); it++)
delete it->second;
size_t RTLIL::Module::count_id(RTLIL::IdString id)
{
- return wires_.count(id) + memories.count(id) + cells.count(id) + processes.count(id);
+ return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
}
#ifndef NDEBUG
}
}
- for (auto &it : cells) {
+ for (auto &it : cells_) {
assert(it.first == it.second->name);
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
for (auto &it : memories)
new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
- for (auto &it : cells)
+ for (auto &it : cells_)
new_mod->addCell(it.first, it.second);
for (auto &it : processes)
{
assert(!cell->name.empty());
assert(count_id(cell->name) == 0);
- cells[cell->name] = cell;
+ cells_[cell->name] = cell;
}
namespace {
void RTLIL::Module::remove(RTLIL::Cell *cell)
{
- assert(cells.count(cell->name) != 0);
- cells.erase(cell->name);
+ assert(cells_.count(cell->name) != 0);
+ cells_.erase(cell->name);
delete cell;
}
void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
{
- assert(cells[cell->name] == cell);
- cells.erase(cell->name);
+ assert(cells_[cell->name] == cell);
+ cells_.erase(cell->name);
cell->name = new_name;
add(cell);
}
assert(count_id(old_name) != 0);
if (wires_.count(old_name))
rename(wires_.at(old_name), new_name);
- else if (cells.count(old_name))
- rename(cells.at(old_name), new_name);
+ else if (cells_.count(old_name))
+ rename(cells_.at(old_name), new_name);
else
log_abort();
}
std::set<RTLIL::IdString> avail_parameters;
std::map<RTLIL::IdString, RTLIL::Wire*> wires_;
std::map<RTLIL::IdString, RTLIL::Memory*> memories;
- std::map<RTLIL::IdString, RTLIL::Cell*> cells;
+ std::map<RTLIL::IdString, RTLIL::Cell*> cells_;
std::map<RTLIL::IdString, RTLIL::Process*> processes;
std::vector<RTLIL::SigSig> connections_;
RTLIL_ATTRIBUTE_MEMBERS
template<typename T>
void RTLIL::Module::rewrite_sigspecs(T functor)
{
- for (auto &it : cells)
+ for (auto &it : cells_)
it.second->rewrite_sigspecs(functor);
for (auto &it : processes)
it.second->rewrite_sigspecs(functor);
log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
// For all ports on all cells
- for (auto &cell_iter : module->cells)
+ for (auto &cell_iter : module->cells_)
for (auto &conn : cell_iter.second->connections())
{
// Get the signals on the port
log("Modules in current design:\n");
for (auto &mod : design->modules)
log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
- mod.second->wires_.size(), mod.second->cells.size());
+ mod.second->wires_.size(), mod.second->cells_.size());
}
} MyPass;
int best_dff_counter = 0;
std::map<std::pair<bool, RTLIL::SigSpec>, int> dff_counters;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_")
mark_port(clk_sig);
std::vector<RTLIL::Cell*> cells;
- cells.reserve(module->cells.size());
- for (auto &it : module->cells)
+ cells.reserve(module->cells_.size());
+ for (auto &it : module->cells_)
if (design->selected(current_module, it.second))
cells.push_back(it.second);
for (auto c : cells)
mark_port(RTLIL::SigSpec(wire_it.second));
}
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
for (auto &port_it : cell_it.second->connections())
mark_port(port_it.second);
std::map<std::string, int> cell_stats;
if (builtin_lib)
{
- for (auto &it : mapped_mod->cells) {
+ for (auto &it : mapped_mod->cells_) {
RTLIL::Cell *c = it.second;
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\ZERO" || c->type == "\\ONE") {
}
else
{
- for (auto &it : mapped_mod->cells)
+ for (auto &it : mapped_mod->cells_)
{
RTLIL::Cell *c = it.second;
cell_stats[RTLIL::unescape_id(c->type)]++;
if (!flag_global)
return;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
if (design->modules.count(it.second->type) == 0)
continue;
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
for (auto &port : it.second->connections_)
if (ct.cell_output(it.second->type, port.first))
sigmap(port.second).replace(sig, dummy_wire, &port.second);
if (flag_nounset)
log_cmd_error("Cant use -port together with -nounset.\n");
- if (module->cells.count(RTLIL::escape_id(port_cell)) == 0)
+ if (module->cells_.count(RTLIL::escape_id(port_cell)) == 0)
log_cmd_error("Can't find cell %s.\n", port_cell.c_str());
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
- module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
+ module->cells_.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
}
else
log_cmd_error("Expected -set, -unset, or -port.\n");
std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map;
SigMap sigmap(module);
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
}
}
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (design->selected(module, it.second))
delete_mems.insert(it.first);
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (design->selected(module, it.second))
delete_cells.insert(it.second);
if ((it.second->type == "$memrd" || it.second->type == "$memwr") &&
return;
}
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (it.first == from_name) {
log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
module->rename(it.second, to_name);
module->wires_.swap(new_wires);
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (it.first[0] == '$' && design->selected(module, it.second))
do it.second->name = stringf("\\_%d_", counter++);
while (module->count_id(it.second->name) > 0);
new_cells[it.second->name] = it.second;
}
- module->cells.swap(new_cells);
+ module->cells_.swap(new_cells);
}
}
else
module->wires_.swap(new_wires);
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (design->selected(module, it.second))
if (it.first[0] == '\\')
it.second->name = NEW_ID;
new_cells[it.second->name] = it.second;
}
- module->cells.swap(new_cells);
+ module->cells_.swap(new_cells);
}
}
else
if (!design->selected(mod_it.second))
continue;
- for (auto &c : mod_it.second->cells)
+ for (auto &c : mod_it.second->cells_)
for (auto &p : c.second->connections_)
{
RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());
if (design->selected(module, it.second))
selectedSignals.add(sigmap(RTLIL::SigSpec(it.second)));
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
for (auto &it : mod->memories)
if (!lhs.selected_member(mod_it.first, it.first))
new_sel.selected_members[mod->name].insert(it.first);
- for (auto &it : mod->cells)
+ for (auto &it : mod->cells_)
if (!lhs.selected_member(mod_it.first, it.first))
new_sel.selected_members[mod->name].insert(it.first);
for (auto &it : mod->processes)
{
if (lhs.selected_whole_module(mod_it.first))
{
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
{
if (design->modules.count(cell_it.second->type) == 0)
continue;
lhs.selected_members[mod->name].insert(it.first);
for (auto &it : mod->memories)
lhs.selected_members[mod->name].insert(it.first);
- for (auto &it : mod->cells)
+ for (auto &it : mod->cells_)
lhs.selected_members[mod->name].insert(it.first);
for (auto &it : mod->processes)
lhs.selected_members[mod->name].insert(it.first);
}
}
- for (auto &cell : mod->cells)
+ for (auto &cell : mod->cells_)
for (auto &conn : cell.second->connections())
{
char last_mode = '-';
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "c:") {
- for (auto &it : mod->cells)
+ for (auto &it : mod->cells_)
if (match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "t:") {
- for (auto &it : mod->cells)
+ for (auto &it : mod->cells_)
if (match_ids(it.second->type, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
for (auto &it : mod->memories)
if (match_attr(it.second->attributes, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
- for (auto &it : mod->cells)
+ for (auto &it : mod->cells_)
if (match_attr(it.second->attributes, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
for (auto &it : mod->processes)
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "r:") {
- for (auto &it : mod->cells)
+ for (auto &it : mod->cells_)
if (match_attr(it.second->parameters, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else {
for (auto &it : mod->memories)
if (match_ids(it.first, arg_memb))
sel.selected_members[mod->name].insert(it.first);
- for (auto &it : mod->cells)
+ for (auto &it : mod->cells_)
if (match_ids(it.first, arg_memb))
sel.selected_members[mod->name].insert(it.first);
for (auto &it : mod->processes)
for (auto &it : mod_it.second->memories)
if (sel->selected_member(mod_it.first, it.first))
LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
- for (auto &it : mod_it.second->cells)
+ for (auto &it : mod_it.second->cells_)
if (sel->selected_member(mod_it.first, it.first))
LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
for (auto &it : mod_it.second->processes)
for (auto &it : mod_it.second->memories)
if (sel->selected_member(mod_it.first, it.first))
total_count++;
- for (auto &it : mod_it.second->cells)
+ for (auto &it : mod_it.second->cells_)
if (sel->selected_member(mod_it.first, it.first))
total_count++;
for (auto &it : mod_it.second->processes)
RTLIL::Module *module = NULL;
if (design->modules.count(design->selected_active_module) > 0)
module = design->modules.at(design->selected_active_module);
- if (module != NULL && module->cells.count(modname) > 0)
- modname = module->cells.at(modname)->type;
+ if (module != NULL && module->cells_.count(modname) > 0)
+ modname = module->cells_.at(modname)->type;
}
if (design->modules.count(modname) > 0) {
RTLIL::Module *module = design->modules.at(design->selected_active_module);
counter += log_matches("wires", pattern, module->wires_);
counter += log_matches("memories", pattern, module->memories);
- counter += log_matches("cells", pattern, module->cells);
+ counter += log_matches("cells", pattern, module->cells_);
counter += log_matches("processes", pattern, module->processes);
}
if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list);
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list);
if (!design->selected(module))
continue;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (design->selected(module, it.second))
do_setunset(it.second->parameters, setunset_list);
}
undriven_signals.add(sigmap(it.second));
CellTypes ct(design);
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
for (auto &conn : it.second->connections())
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
undriven_signals.del(sigmap(conn.second));
fprintf(f, "}\n");
}
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
if (!design->selected_member(module->name, it.first))
continue;
log("Skipping blackbox module %s.\n", id2cstr(module->name));
continue;
} else
- if (module->cells.empty() && module->connections().empty() && module->processes.empty()) {
+ if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) {
log("Skipping empty module %s.\n", id2cstr(module->name));
continue;
} else
for (auto &mod_it : design->modules) {
if (mod_it.second->get_bool_attribute("\\blackbox"))
continue;
- if (mod_it.second->cells.empty() && mod_it.second->connections().empty())
+ if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())
continue;
if (design->selected_module(mod_it.first))
modcount++;
driven_bits.push_back(RTLIL::State::Sm);
}
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
for (auto &conn : it.second->connections())
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
RTLIL::SigSpec sig = sigmap(conn.second);
if (design->selected(module, it.second))
selected_bits.add(sigmap(it.second));
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (!sel_by_wire && !design->selected(module, it.second))
continue;
for (auto &conn : it.second->connections_)
std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
- for (auto &c : module->cells)
+ for (auto &c : module->cells_)
for (auto &p : c.second->connections())
{
if (!ct.cell_known(c.second->type))
num_memory_bits += it.second->width * it.second->size;
}
- for (auto &it : mod->cells) {
+ for (auto &it : mod->cells_) {
if (!design->selected(mod, it.second))
continue;
num_cells++;
sig2driver.clear();
sig2user.clear();
sig_at_port.clear();
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
for (auto &conn_it : cell_it.second->connections()) {
if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.set(module);
ct.setup_internals();
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *c = cell_it.second;
if (ct.cell_known(c->type) && design->selected(mod, c))
for (auto &p : c->connections()) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells;
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
fsm_cells.push_back(cell_it.second);
for (auto c : fsm_cells) {
for (auto &mod_it : design->modules)
if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
attr_it = cell_it.second->attributes.find("\\fsm_export");
if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) {
std::set<sig2driver_entry_t> cellport_list;
sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list) {
- RTLIL::Cell *cell = module->cells.at(cellport.first);
+ RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
return false;
std::set<sig2driver_entry_t> cellport_list;
sig2driver.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
- RTLIL::Cell *cell = module->cells.at(cellport.first);
+ RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
continue;
log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
cellport_list.clear();
sig2trigger.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
- RTLIL::Cell *cell = module->cells.at(cellport.first);
+ RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
cellport_list.clear();
sig2driver.find(ctrl_out, cellport_list);
for (auto &cellport : cellport_list) {
- RTLIL::Cell *cell = module->cells.at(cellport.first);
+ RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size());
sig2driver.clear();
sig2trigger.clear();
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
for (auto &conn_it : cell_it.second->connections()) {
if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
RTLIL::SigSpec sig = conn_it.second;
for (auto &mod_it : design->modules)
if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
log("\n");
log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str());
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells;
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
fsm_cells.push_back(cell_it.second);
for (auto cell : fsm_cells)
for (auto &mod_it : design->modules) {
if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second))
FsmData::optimize_fsm(cell_it.second, mod_it.second);
}
for (auto &mod_it : design->modules)
if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, default_encoding);
std::set<std::string> found_celltypes;
for (auto i1 : design->modules)
- for (auto i2 : i1.second->cells)
+ for (auto i2 : i1.second->cells_)
{
RTLIL::Cell *cell = i2.second;
if (cell->type[0] == '$' || design->modules.count(cell->type) > 0)
log("Generate module for cell type %s:\n", celltype.c_str());
for (auto i1 : design->modules)
- for (auto i2 : i1.second->cells)
+ for (auto i2 : i1.second->cells_)
if (i2.second->type == celltype) {
for (auto &conn : i2.second->connections()) {
if (conn.first[0] != '$')
std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
std::string filename;
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
log("Used module: %*s%s\n", indent, "", mod->name.c_str());
used.insert(mod);
- for (auto &it : mod->cells) {
+ for (auto &it : mod->cells_) {
if (design->modules.count(it.second->type) > 0)
hierarchy_worker(design, used, design->modules[it.second->type], indent+4);
}
std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
for (auto &mod_it : design->modules)
- for (auto &cell_it : mod_it.second->cells) {
+ for (auto &cell_it : mod_it.second->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (design->modules.count(cell->type) == 0)
continue;
flag_signal(conn.second, true, true, true, false, false);
}
}
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
if (submod.cells.count(cell) > 0)
continue;
for (auto &it : module->wires_)
it.second->attributes.erase("\\submod");
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) {
}
else
{
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (!design->selected(module, cell))
std::vector<RTLIL::Cell*> del_cells;
std::vector<RTLIL::Cell*> memcells;
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name)
memcells.push_back(cell);
if (bit.wire == NULL)
continue;
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$dff") {
RTLIL::SigSpec new_q = cell->get("\\Q");
static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only)
{
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
if (!design->selected(module, cell_it.second))
continue;
if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::Cell*> cells;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (it.second->type == "$mem" && design->selected(module, it.second))
cells.push_back(it.second);
for (auto cell : cells)
non_feedback_nets.insert(bits.begin(), bits.end());
}
- for (auto cell_it : module->cells)
+ for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
bool ignore_data_port = false;
std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
sigmap_xmux = sigmap;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::IdString> memcells;
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second))
memcells.push_back(cell_it.first);
for (auto &it : memcells)
- handle_memory(module, module->cells.at(it));
+ handle_memory(module, module->cells_.at(it));
}
struct MemoryUnpackPass : public Pass {
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
SigSet<RTLIL::Cell*> wire2driver;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
for (auto &it2 : cell->connections()) {
if (!ct.cell_input(cell->type, it2.first)) {
SigPool connected_signals;
if (!purge_mode)
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
if (ct_reg.cell_known(cell->type))
for (auto &it2 : cell->connections())
SigMap assign_map(module);
std::set<RTLIL::SigSpec> direct_sigs;
std::set<RTLIL::Wire*> direct_wires;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
if (ct_all.cell_known(cell->type))
for (auto &it2 : cell->connections())
SigPool used_signals;
SigPool used_signals_nodrivers;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
for (auto &it2 : cell->connections_) {
assign_map.apply(it2.second);
SigPool used_signals;
SigPool all_signals;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
for (auto &conn : it.second->connections()) {
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
driven_signals.add(sigmap(conn.second));
std::map<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
std::vector<RTLIL::Cell*> cells;
- cells.reserve(module->cells.size());
- for (auto &cell_it : module->cells)
+ cells.reserve(module->cells_.size());
+ for (auto &cell_it : module->cells_)
if (design->selected(module, cell_it.second)) {
if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") &&
cell_it.second->get("\\A").size() == 1 && cell_it.second->get("\\Y").size() == 1)
// .ctrl_sigs
// .input_sigs
// .const_activated
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
did_something = true;
SigPool mem_wren_sigs;
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mem")
mem_wren_sigs.add(assign_map(cell->get("\\WR_EN")));
if (cell->type == "$memwr")
mem_wren_sigs.add(assign_map(cell->get("\\EN")));
}
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q"))))
mem_wren_sigs.add(assign_map(cell->get("\\D")));
bool keep_expanding_mem_wren_sigs = true;
while (keep_expanding_mem_wren_sigs) {
keep_expanding_mem_wren_sigs = false;
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) {
if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) ||
SigSet<RTLIL::Cell*> drivers;
std::set<RTLIL::Cell*> cells;
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type != type || !design->selected(module, cell))
continue;
std::vector<RTLIL::Cell*> cells;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second))
cells.push_back(it.second);
mux_drivers.clear();
std::vector<std::string> dff_list;
- for (auto &it : mod_it.second->cells) {
+ for (auto &it : mod_it.second->cells_) {
if (it.second->type == "$mux" || it.second->type == "$pmux") {
if (it.second->get("\\A").size() == it.second->get("\\B").size())
mux_drivers.insert(assign_map(it.second->get("\\Y")), it.second);
}
for (auto &id : dff_list) {
- if (mod_it.second->cells.count(id) > 0 &&
- handle_dff(mod_it.second, mod_it.second->cells[id]))
+ if (mod_it.second->cells_.count(id) > 0 &&
+ handle_dff(mod_it.second, mod_it.second->cells_[id]))
total_count++;
}
}
cell_hash_cache.clear();
#endif
std::vector<RTLIL::Cell*> cells;
- cells.reserve(module->cells.size());
- for (auto &it : module->cells) {
+ cells.reserve(module->cells_.size());
+ for (auto &it : module->cells_) {
if (ct.cell_known(it.second->type) && design->selected(module, it.second))
cells.push_back(it.second);
}
if (signal == ref)
return true;
- for (auto &cell_it : mod->cells) {
+ for (auto &cell_it : mod->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);
SatGen satgen(&ez, &sigmap);
satgen.model_undef = model_undef;
- for (auto &c : module->cells)
+ for (auto &c : module->cells_)
if (!satgen.importCell(c.second))
log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
SigMap sigmap(module);
SigPool dffsignals;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (ct.cell_known(it.second->type) && it.second->has("\\Q"))
dffsignals.add(sigmap(it.second->get("\\Q")));
}
std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
SigMap sigmap(module);
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
if (!design->selected(module, it.second))
continue;
shared_wires.insert(it.first);
if (flag_evert)
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second))
shared_cells.insert(it.first);
{
RTLIL::Cell *cell;
- if (module->cells.count(it) == 0)
+ if (module->cells_.count(it) == 0)
goto delete_shared_cell;
- cell = module->cells.at(it);
+ cell = module->cells_.at(it);
if (!design->selected(module, cell))
goto delete_shared_cell;
if (!consider_cell(design, dff_cells[module], cell))
goto delete_shared_cell;
- if (!compare_cells(first_module->cells.at(it), cell))
+ if (!compare_cells(first_module->cells_.at(it), cell))
goto delete_shared_cell;
if (0)
if (flag_cut)
{
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (!ct.cell_known(it.second->type))
continue;
for (auto &conn : it.second->connections_)
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
for (auto &cell_name : info.cells) {
- RTLIL::Cell *cell = module->cells.at(cell_name);
+ RTLIL::Cell *cell = module->cells_.at(cell_name);
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector();
for (auto &bit : cell_q_bits)
if (wire_bits_set.count(bit))
{
std::vector<RTLIL::Cell*> delete_cells;
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
if (flag_shared) {
if (shared_cells.count(it.first) == 0)
batches.push_back(sigmap(it.second).to_sigbit_set());
bits_full_total += it.second->width;
}
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (ct.cell_known(it.second->type)) {
std::set<RTLIL::SigBit> inputs, outputs;
for (auto &port : it.second->connections()) {
}
int import_cell_counter = 0;
- for (auto &c : module->cells)
+ for (auto &c : module->cells_)
if (design->selected(module, c.second)) {
// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
if (satgen.importCell(c.second, timestep)) {
queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
if (!fwd_ct.cell_known(it.second->type)) {
std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
queue_bits.insert(bits.begin(), bits.end());
void find_shareable_cells()
{
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
log("Mapping DFF cells in module `%s':\n", module->name.c_str());
std::vector<RTLIL::Cell*> cell_list;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
cell_list.push_back(it.second);
}
std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
if (max_fanout > 0)
- for (auto &cell_it : mod->cells)
+ for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (!sel || sel->selected(mod, cell))
}
// create graph nodes from cells
- for (auto &cell_it : mod->cells)
+ for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (sel && !sel->selected(mod, cell))
}
// mark external signals (used in non-selected cells)
- for (auto &cell_it : mod->cells)
+ for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (sel && !sel->selected(mod, cell))
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> delete_cells;
- for (auto &cell_it : mod_it.second->cells) {
+ for (auto &cell_it : mod_it.second->cells_) {
if (mappers.count(cell_it.second->type) == 0)
continue;
if (!design->selected(mod_it.second, cell_it.second))
std::string orig_cell_name;
if (!flatten_mode)
- for (auto &it : tpl->cells)
+ for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") {
orig_cell_name = cell->name;
module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
}
}
- for (auto &it : tpl->cells)
+ for (auto &it : tpl->cells_)
{
RTLIL::IdString c_name = it.second->name;
std::vector<std::string> cell_names;
SigMap sigmap(module);
- for (auto &cell_it : module->cells)
+ for (auto &cell_it : module->cells_)
cell_names.push_back(cell_it.first);
for (auto &cell_name : cell_names)
{
- if (module->cells.count(cell_name) == 0)
+ if (module->cells_.count(cell_name) == 0)
continue;
- RTLIL::Cell *cell = module->cells[cell_name];
+ RTLIL::Cell *cell = module->cells_[cell_name];
if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
continue;
projects / yosys.git / commitdiff